VHDL nbit - 4 bit tri state buffer structural design code test in circuit and test bench ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

This is another components which will be used to construct the datapath. Refer to the lab sheets(lab 3) :

VHDL code

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity nbittristatebuffer is  
 generic(n:positive:=4);  
   Port ( datain : in STD_LOGIC_VECTOR (n-1 downto 0);  
       enable : in STD_LOGIC;  
       output : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end nbittristatebuffer;  
 architecture Behavioral of nbittristatebuffer is  
                component tri_buff   
                      Port ( Input : in std_logic;  
                                enable : in std_logic;  
                                Output : out std_logic);  
                end component;  
 begin  
                inst:for i in n-1 downto 0 generate  
                A: tri_buff port map(datain(i),enable,output(i));  
                end generate;  
 end Behavioral;  

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY nbittristatebuffertest IS  
 END nbittristatebuffertest;  
 ARCHITECTURE behavior OF nbittristatebuffertest IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT nbittristatebuffer  
   PORT(  
      datain : IN std_logic_vector(3 downto 0);  
      enable : IN std_logic;  
      output : OUT std_logic_vector(3 downto 0)  
     );  
   END COMPONENT;  
   --Inputs  
   signal datain : std_logic_vector(3 downto 0) := (others => '0');  
   signal enable : std_logic := '0';  
       --Outputs  
   signal output : std_logic_vector(3 downto 0);  
   -- No clocks detected in port list. Replace <clock> below with   
   -- appropriate port name   
   constant <clock>_period : time := 10 ns;  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: nbittristatebuffer PORT MAP (  
      datain => datain,  
      enable => enable,  
      output => output  
     );  
   -- Stimulus process  
   stim_proc: process  
   begin            
    -- hold reset state for 100 ns.  
    wait for 100 ns;       
  datain <= "1001";  
     wait for 100 ns;       
            enable <= '0' ;  
            wait for 100 ns;       
            enable <= '1' ;  
               wait for 100 ns;       
    wait;  
   end process;  
 END;  

Component ( 1 bit tri state buffer )