VHDL 4 bit shifter rotator Structural design using components code ISE design suite Xilinx spartan 3 waveshare development board

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:
http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

 

Parts working on now (shifter):

This is another components which will be used to construct the datapath. Refer to the lab sheets:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 ---------------------------------------------------------  
 -- Top level design  
 ---------------------------------------------------------  
 entity nBitShiftRotateM is  
   generic(n:positive:=4);  
       Port (Data_In1 : in std_logic_vector(n-1 downto 0);  
             Data_In2 : in std_logic_vector(n-1 downto 0);  
             Right_In : in std_logic;  
             Right_Select : in std_logic;  
             Left_In : in std_logic;  
             Left_Select : in std_logic;  
             Control : in std_logic_vector (1 downto 0);  
          Output : out std_logic_vector (n-1 downto 0));  
 end nBitShiftRotateM;  
 ---------------------------------------------------------  
 -- Top level design  
 ---------------------------------------------------------  
 architecture Behavioral of nBitShiftRotateM is  
 --COMPONENT: two_input_mux  
 component twoinputmultiplexer   
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       s : in STD_LOGIC;  
                 output : out STD_LOGIC);  
 end component;  
 --END COMPONENT: two_input_mux  
 --COMPONENT: fourInputMux  
 component fourinputmux   
 port (  
    a : in std_logic;  
    b : in std_logic;  
    c : in std_logic;  
    d : in std_logic;  
    control : in std_logic_vector(1 downto 0);  
    output : out std_logic  
    );  
 end component;  
 --END COMPONENT: fourInputMux  
 --SIGNALS  
 signal muxToFour, muxToFourZero: std_logic;  
 begin  
      inst: for i in n-1 downto 0 generate  
                          if1: if i = n-1 generate  
                               twoMux: twoinputmultiplexer port map (Data_In1(0),Left_In, Left_Select, muxToFour);  
                               fourMuxTwo: fourinputmux port map (Data_In1(i), Data_In1(i-1), muxToFour, Data_In2(i), Control, Output(i));  
                          end generate;  
                          --When i is 0  
                          if2: if i = 0 generate  
                               twoMuxZero: twoinputmultiplexer port map (Data_In1(n-1),Right_In, Right_Select, muxToFourZero);  
                               fourMuxZero: fourinputmux port map (Data_In1(0),muxToFourZero, Data_In1(1), Data_In2(0), Control, Output(0));  
                          end generate;  
                          --Else generate  
                          if3: if ((i/=0) and (i/=n-1)) generate  
                               fourMuxMid: fourinputmux port map (Data_In1(i),Data_In1(i-1), Data_In1(i+1), Data_In2(i), Control, Output(i));  
                          end generate;  
      end generate;  
 end Behavioral;  

Component (1 bit  2 input multiplexer ) code in the description of the video

library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity twoinputmultiplexer is  
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       s : in STD_LOGIC;  
                 output : out STD_LOGIC);  
 end twoinputmultiplexer;  
 architecture Behavioral of twoinputmultiplexer is  
 begin  
 process(a,b,s)  
 begin  
           case s is  
            when '0' => output <= a;  
            when '1' => output <= b;  
            when others => output <= b;  
           end case;  
 end process;  
 end Behavioral;  
 --s a b output  
 --0 0 0  0  
 --0 0 1  0  
 --0 1 0  1   
 --0 1 1  1  
 --1 0 0  0  
 --1 0 1  1  
 --1 1 0  0  
 --1 1 1  1  

 Component ( four input multiplexer ) code in the description of the video