VHDL three input or gate code test in circuit and test bench

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:
http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP


Intended design:

Datapath and controller internals:

     

Parts working on now:

Constructing the alu:

For constructing the ALU we need an adder, the adder is formed by two half adders and the half adder is formed with gates. Refer to the lab sheets:  

Testbench: 

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY three_or_gate_test IS  
 END three_or_gate_test;  
 ARCHITECTURE behavior OF three_or_gate_test IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT threeinputorgate  
   PORT(  
      a : IN std_logic;  
      b : IN std_logic;  
      c : IN std_logic;  
      f : OUT std_logic  
     );  
   END COMPONENT;  
   --Inputs  
   signal a : std_logic := '0';  
   signal b : std_logic := '0';  
   signal c : std_logic := '0';  
       --Outputs  
   signal f : std_logic;  
   -- No clocks detected in port list. Replace <clock> below with   
   -- appropriate port name   
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: threeinputorgate PORT MAP (  
      a => a,  
      b => b,  
      c => c,  
      f => f  
     );  
   -- Clock process definitions  
   -- Stimulus process  
   stim_proc: process  
   begin            
    -- hold reset state for 100 ns.  
    wait for 100 ns;       
           wait for 100 ns; -- wait for global reset  
  a <= '0'; -- check 0 nand 0 = 1  
  b <= '0';   
  c <= '0';   
  wait for 100 ns;  
  a <= '0';   
  b <= '0';   
  c <= '1';   
  wait for 100 ns;  
  a <= '0';   
  b <= '1';   
  c <= '0';   
  wait for 100 ns;  
  a <= '0';  
  b <= '1';   
  c <= '1';   
  wait; --   
  a <= '1';   
  b <= '0';   
  c <= '0';   
  wait for 100 ns;  
  a <= '1';   
  b <= '0';   
  c <= '1';   
  wait for 100 ns;  
  a <= '1';   
  b <= '1';   
  c <= '0';   
  wait for 100 ns;  
  a <= '1';   
  b <= '1';   
  c <= '1';   
  wait for 100 ns;  
    wait;  
   end process;  
 END;  

VHDL  code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity threeinputorgate is  
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       c : in STD_LOGIC;  
       f : out STD_LOGIC);  
 end threeinputorgate;  
 architecture Behavioral of threeinputorgate is  
 begin  
 f<= (a or b or c);  
 end Behavioral;