VHDL 4 bit logic unit Structural design code test on circuit and test bench ISE design suite Xilinx spartan 3 waveshare development board

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now (ALU):

This is another components which will be used to construct the datapath. Refer to the lab sheets:

 VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity nbitlogicunit is  
 generic(n:positive:=4);  
   Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);  
       InB : in STD_LOGIC_VECTOR (n-1 downto 0);  
       control : in STD_LOGIC_VECTOR (1 downto 0);  
       output : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end nbitlogicunit;  
 architecture Behavioral of nbitlogicunit is  
 component bitsliceLogicslice   
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       control : in STD_LOGIC_VECTOR (1 downto 0);  
       output : out STD_LOGIC);  
 end component;  
 begin  
 inst: for i in n-1 downto 0 generate  
 A: bitsliceLogicslice port map(InA(i),InB(i),control,output(i));  
 end generate;  
 end Behavioral;  

Test bench:

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY nbitlogicunittestbench IS  
 END nbitlogicunittestbench;  
 ARCHITECTURE behavior OF nbitlogicunittestbench IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT nbitlogicunit  
   PORT(  
      InA : IN std_logic_vector(3 downto 0);  
      InB : IN std_logic_vector(3 downto 0);  
      control : IN std_logic_vector(1 downto 0);  
      output : OUT std_logic_vector(3 downto 0)  
     );  
   END COMPONENT;  
   --Inputs  
   signal InA : std_logic_vector(3 downto 0) := (others => '0');  
   signal InB : std_logic_vector(3 downto 0) := (others => '0');  
   signal control : std_logic_vector(1 downto 0) := (others => '0');  
       --Outputs  
   signal output : std_logic_vector(3 downto 0);  
   -- No clocks detected in port list. Replace <clock> below with   
   -- appropriate port name   
   constant <clock>_period : time := 10 ns;  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: nbitlogicunit PORT MAP (  
      InA => InA,  
      InB => InB,  
      control => control,  
      output => output  
     );  
   -- Clock process definitions  
   stim_proc :process  
   begin  
       wait for 100 ns; -- wait for global reset  
  a <= "0000"; -- check not gate input 0 output 1  
  control <= "00"; -- check 0 nand 0 = 1  
  wait for 100 ns; -- wait for global reset  
  a <= "1111"; --and gate output should be 1110  
  b <= "1110";  
  control <= "01"; -- check 0 and 0 = 1  
  wait for 100 ns;  
  a <= "1101"; -- xor gate output should be 1100   
  b <= "0001";  
  control <= "10"; -- check 0 nand 0 = 1  
  wait for 100 ns; -- wait for global reset  
 a <= "1010"; -- or gate output should be 1011  
  b <= "1011";  
  control <= "11"; -- check 0 nand 0 = 1  
    wait;  
   end process;  
 END;  

Component ( 1bit logic slice ) code in the video description