VHDL nbit register - 4 bit register structural design code test in circuit and test bench ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now (ALU):

This is another components which will be used to construct the datapath. Refer to the lab sheets:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity nbitregister is  
 generic(n:positive:=4);  
   Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       preset : in STD_LOGIC;  
       q : out STD_LOGIC_VECTOR (n-1 downto 0);  
       qnot : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end nbitregister;  
 architecture Behavioral of nbitregister is  
 component D_flipflop   
 port (d, clk, reset, preset : in std_logic;  
           q,qnot: out std_logic);  
 end component;  
 begin  
 inst:for i in n-1 downto 0 generate  
 A: D_flipflop port map(Dinputs(i),CLK,reset,preset,q(i),qnot(i));  
 end generate;  
 end Behavioral;  

Test bench

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY nbitregistertestbench IS  
 END nbitregistertestbench;  
 ARCHITECTURE behavior OF nbitregistertestbench IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT nbitregister  
   PORT(  
      Dinputs : IN std_logic_vector(3 downto 0);  
      CLK : IN std_logic;  
      reset : IN std_logic;  
      preset : IN std_logic;  
      q : OUT std_logic_vector(3 downto 0);  
      qnot : OUT std_logic_vector(3 downto 0)  
     );  
   END COMPONENT;  
   --Inputs  
   signal Dinputs : std_logic_vector(3 downto 0) := (others => '0');  
   signal CLK : std_logic := '0';  
   signal reset : std_logic := '0';  
   signal preset : std_logic := '0';  
       --Outputs  
   signal q : std_logic_vector(3 downto 0);  
   signal qnot : std_logic_vector(3 downto 0);  
   -- Clock period definitions  
   constant CLK_period : time := 10 ns;  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: nbitregister PORT MAP (  
      Dinputs => Dinputs,  
      CLK => CLK,  
      reset => reset,  
      preset => preset,  
      q => q,  
      qnot => qnot  
     );  
  clk <= not clk after 50 ns; -- period = 100ns  
           tb : PROCESS  
      BEGIN  
                wait for 100 ns;  
                reset <= '1';  
                wait for 120 ns;  
                reset <= '0';  
                wait for 120 ns;  
                preset <= '1';  
                wait for 120 ns;  
                preset <= '0';  
                wait for 120 ns;  
                Dinputs <= "1111";  
                wait for 120 ns;  
                Dinputs <= "0000";  
                wait for 120 ns;   
    wait;  
   end process;  
 END;  

Component ( D flip flop ) code in the video description

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE