VHDL shift control logic code and test on circuit and test bench ISE design suite Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:
http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

 

Parts working on now (datapath):

This is another components which will be used to construct the datapath. Refer to the lab sheets:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity shiftcontrollogic is  
   Port ( input : in STD_LOGIC_VECTOR (2 downto 0);  
       output : out STD_LOGIC_VECTOR (1 downto 0));  
 end shiftcontrollogic;  
 architecture Behavioral of shiftcontrollogic is  
 begin  
 output(0)<= (not input(2)) and (input(1) or input(0));  
 output(1)<= ( input(2)) and (input(1) or input(0));  
 end Behavioral;  
 -- i2    i1    i0    f1   f0  
 ---0     0     0      0      0  
 ---0     0     1      0      1  
 ---0     1     0      0      1  
 ---0     1     1      0      1  
 ---1     0     0      0      0  
 ---1     0     1      1      0  
 ---1     1     0      1      0  
 ---1     1     1      1      0  

TEST bench code:

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY ShitControlLogicTest IS  
 END ShitControlLogicTest;  
 ARCHITECTURE behavior OF ShitControlLogicTest IS  
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT shiftcontrollogic  
    Port ( input : in STD_LOGIC_VECTOR (2 downto 0);  
       output : out STD_LOGIC_VECTOR (1 downto 0));  
   END COMPONENT;  
 --input  
   signal input : std_logic_vector(1 downto 0) := (others => '0');  
 --output   
   signal output : std_logic_vector(1 downto 0) ;  
 BEGIN  
   -- Instantiate the Unit Under Test (UUT)  
   uut: shiftcontrollogic PORT MAP (  
      input => input,  
      output => output  
       );  
   -- Stimulus process  
   stim_proc: process  
   begin      
  wait for 100 ns;  
  input <= "000";  
  wait for 100 ns;  
  input <= "001";  
  wait for 100 ns;  
  input <= "010";  
  wait for 100 ns;  
  input <= "011";  
  wait for 100 ns;  
  input <= "100";  
  wait for 100 ns;  
  input <= "101";  
  wait for 100 ns;  
  input <= "110";  
  wait for 100 ns;  
  input <= "111";  
   end process;  
 END;