VHDL 1 bit 4 input multiplexer code and test on circuit and test bench ISE design suite Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:
http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The video complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

   

Parts working on now (datapath):

This is another components which will be used to construct the datapath. Refer to the lab sheets:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity fourinputmux is  
 port (  
    a : in std_logic;  
    b : in std_logic;  
    c : in std_logic;  
    d : in std_logic;  
    control : in std_logic_vector(1 downto 0);  
    output : out std_logic  
    );  
 end fourinputmux ;  
 architecture Behavioral of fourinputmux is  
 begin  
                process(a,b,c,d,control)  
                          begin  
                                    case control is  
                                     when "00" => output <= a;  
                                     when "01" => output <= b;  
                                     when "10" => output <= c;  
                                     when others => output <= d;  
                                    end case;  
                end process;  
 end Behavioral;  
 --   INPUTS               OUTPUT  
 --Control      a        b        c        d      output  
 --0      0           0        x           x           x           0  
 --0      0           1           x           x           x           1  
 --0      1           x           0           x           x           0  
 --0      1           x           1           x           x           1  
 --1      0           x           x           0           x           0  
 --1      0           x           x           1           x           1  
 --1      1           x           x           x           0           0  
 --1      1           x           x           x           1           1  

Test Bench code:

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY MUX4inputtest IS  
 END MUX4inputtest;  
 ARCHITECTURE behavior OF MUX4inputtest IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT fourinputmux  
   port (  
    a : in std_logic;  
    b : in std_logic;  
    c : in std_logic;  
    d : in std_logic;  
    control : in std_logic_vector(1 downto 0);  
    output : out std_logic  
    );  
 end fourinputmux ;  
                     signal a : std_logic := '0';  
                     signal b : std_logic := '0';  
                     signal c : std_logic := '0';  
                     signal d : std_logic := '0';  
                     signal control : std_logic_vector(1 downto 0) := (others => '0');  
       --Outputs  
                     signal output : std_logic;  
 BEGIN  
 uut: fourinputmux PORT MAP (  
      a => a,  
      b => b ,  
      c => c ,  
      d => d,  
            control=> control,  
      output => output  
     );       
 wait for 100 ns;  
     control <= "00";  
           a <= '0';  
           wait for 100 ns;  
           control <= "00";  
           a <= '1';  
           wait for 100 ns;  
           control <= "01";  
           b <= '0';  
           wait for 100 ns;  
           control <= "01";  
           b <= '1';  
           wait for 100 ns;  
           control <= "10";  
           c <= '0';  
           wait for 100 ns;  
           control <= "10";  
           c <= '1';  
           wait for 100 ns;  
           control <= "11";  
           d <= '0';  
           wait for 100 ns;  
           control <= "11";  
           d <= '1';  
   end process;  
 END;