VHDL 4 bit full adder structural design unit code test on circuit and test bench ISE design suite Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now (ALU):

This is another components which will be used to construct the datapath. Refer to the lab sheets:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 entity nbitadder is  
 generic(n:positive:=4);  
   Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);  
       InB : in STD_LOGIC_VECTOR (n-1 downto 0);  
       C_terms : in STD_LOGIC_VECTOR (n-1 downto 0);  
       sum : out STD_LOGIC_VECTOR (n-1 downto 0);  
       c_out : out STD_LOGIC);  
 end nbitadder;  
 architecture Behavioral of nbitadder is  
           component fulladder  
                 Port ( a : in STD_LOGIC;  
                           b : in STD_LOGIC;  
                           cin : in STD_LOGIC;  
                           sum : out STD_LOGIC;  
                           cout : out STD_LOGIC);  
           end component;  
 signal not_connected: STD_LOGIC_VECTOR(n-2 downto 0);  
 begin  
                     inst:for i in n-1 downto 0 generate  
                                    lastbit:if i=n-1 generate  
                                    A: fulladder port map (InA(i),InB(i),C_terms(i),sum(i),c_out);  
                                    end generate;  
                                    otherbits: if i/=n-1 generate  
                                    B: fulladder port map(InA(i),InB(i),C_terms(i),sum(i),not_connected(i));  
                                    end generate;  
                     end generate;  
 end Behavioral;  

Test bench:

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY nbitaddertestbench IS  
 END nbitaddertestbench;  
 ARCHITECTURE behavior OF nbitaddertestbench IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT nbitadder  
   PORT(  
      InA : IN std_logic_vector(3 downto 0);  
      InB : IN std_logic_vector(3 downto 0);  
      C_terms : IN std_logic_vector(3 downto 0);  
      sum : OUT std_logic_vector(3 downto 0);  
      c_out : OUT std_logic  
     );  
   END COMPONENT;  
   --Inputs  
   signal InA : std_logic_vector(3 downto 0) := (others => '0');  
   signal InB : std_logic_vector(3 downto 0) := (others => '0');  
   signal C_terms : std_logic_vector(3 downto 0) := (others => '0');  
       --Outputs  
   signal sum : std_logic_vector(3 downto 0);  
   signal c_out : std_logic;  
   -- No clocks detected in port list. Replace <clock> below with   
   -- appropriate port name   
   constant <clock>_period : time := 10 ns;  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: nbitadder PORT MAP (  
      InA => InA,  
      InB => InB,  
      C_terms => C_terms,  
      sum => sum,  
      c_out => c_out  
     );  
   -- Clock process definitions  
   <clock>_process :process  
   begin  
           <clock> <= '0';  
           wait for <clock>_period/2;  
           <clock> <= '1';  
           wait for <clock>_period/2;  
   end process;  
   -- Stimulus process  
   stim_proc: process  
   begin            
    wait for 100 ns;  
           InA <= "0000";  
    InB <= "0000";  
    C_terms <= "0000";  
    sum <= "0000";  
           wait for 100 ns;  
           InA <= "0000";  
    InB <= "0001";  
    C_terms <= "0000";  
    sum <= "0001";  
           wait for 100 ns;  
       InA <= "0001";  
    InB <= "0001";  
    C_terms <= "0000";  
    sum <= "0000";  
           wait for 100 ns;  
           InA <= "0010";  
    InB <= "0001";  
    C_terms <= "0000";  
    sum <= "0001";  
           wait for 100 ns;  
           InA <= "0010";  
    InB <= "0011";  
    C-Terms <= "0000";  
    sum <= "0001";  
    wait;  
   end process;  
 END;  

Component ( 1 bit full adder ) code in the video description