VHDL 4 bit two input multiplexer Structural design using components test bench xilinx spartan 3

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:
http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

This tutorial uses components to understand the basics of microcontroller design.

Intended design:

Datapath and controller internals:

     

Parts working on now:

n-bit two input mux:

 VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity nbittwoinputmux is  
 generic(n:positive:=4);  
   Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);  
       InB : in STD_LOGIC_VECTOR (n-1 downto 0);  
       Control : in STD_LOGIC;  
       Output : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end nbittwoinputmux;  
 architecture Behavioral of nbittwoinputmux is  
 component twoinputmultiplexer   
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       s : in STD_LOGIC;  
                 output : out STD_LOGIC);  
 end component;  
 begin  
 inst: for i in n-1 downto 0 generate  
 A: twoinputmultiplexer port map(InA(i),InB(i),Control,Output(i));  
 end generate;  
 end Behavioral;  

1 bit 2 input multiplexer COMPONENT

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity twoinputmultiplexer is  
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       s : in STD_LOGIC;  
                 output : out STD_LOGIC);  
 end twoinputmultiplexer;  
 architecture Behavioral of twoinputmultiplexer is  
 begin  
                     process(a,b,s)  
                     begin  
                               case s is  
                                when '0' => output <= a;  
                                when '1' => output <= b;  
                                when others => output <= b;  
                               end case;  
                     end process;  
 end Behavioral;  
 --s a b output  
 --0 0 0  0  
 --0 0 1  0  
 --0 1 0  1   
 --0 1 1  1  
 --1 0 0  0  
 --1 0 1  1  
 --1 1 0  0  
 --1 1 1  1  

four input multiplexer Testbench

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 -- arithmetic functions with Signed or Unsigned values  
 --USE ieee.numeric_std.ALL;  
 ENTITY nBit2InMuxTB IS  
 END nBit2InMuxTB;  
 ARCHITECTURE behavior OF nBit2InMuxTB IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT nbittwoinputmux  
   PORT(  
      InA : IN std_logic_vector(3 downto 0);  
      InB : IN std_logic_vector(3 downto 0);  
      Control : IN std_logic;  
      Output : OUT std_logic_vector(3 downto 0)  
     );  
   END COMPONENT;  
   --Inputs  
   signal InA : std_logic_vector(3 downto 0) := (others => '0');  
   signal InB : std_logic_vector(3 downto 0) := (others => '0');  
   signal Control : std_logic := '0';  
       --Outputs  
   signal Output : std_logic_vector(3 downto 0);  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: nbittwoinputmux PORT MAP (  
      InA => InA,  
      InB => InB,  
      Control => Control,  
      Output => Output  
     );  
   -- Stimulus process  
   stim_proc: process  
   begin            
    -- hold reset state for 100 ns.  
    wait for 100 ns;       
           InA <= "0001";  
           InB <= "0011";  
           Control <= '0';  
           wait for 100 ns;  
           InA <= "0001";  
           InB <= "0011";  
           Control <= '1';  
    wait;  
   end process;  
 END;