This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.
The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:
Lab Sheets:
http://viahold.com/y37
Lab guide
http://cogismith.com/1OwP
The design in this lab covers the basics of microcontrolller structural design
Intended Controlled datapath design design:
Datapath and controller internals:
Parts working on now (shifter):
VHDL code:
Test bench code:
Component ( Shift control logic ) code in the description of the video
Component ( 4 bit shifter rotator ) code in the description of the video
The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:
Lab Sheets:
http://viahold.com/y37
Lab guide
http://cogismith.com/1OwP
The design in this lab covers the basics of microcontrolller structural design
Intended Controlled datapath design design:
Datapath and controller internals:
Parts working on now (shifter):
This is another components which will be used to construct the datapath. Refer to the lab sheets:
VHDL code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ENTITY
entity four_bit_shifter is
Port ( Data_In : in std_logic_vector(3 downto 0);
G : in std_logic_vector(2 downto 0);
Output : out std_logic_vector(3 downto 0));
end four_bit_shifter;
-- ARCHITECTURE
architecture Behavioral of four_bit_shifter is
-- COMPONENTS
component nBitShiftRotateM
generic(n:positive:=4);
Port (Data_In1 : in std_logic_vector(n-1 downto 0);
Data_In2 : in std_logic_vector(n-1 downto 0);
Right_In : in std_logic;
Right_Select : in std_logic;
Left_In : in std_logic;
Left_Select : in std_logic;
Control : in std_logic_vector (1 downto 0);
Output : out std_logic_vector (n-1 downto 0));
end component;
component shiftcontrollogic
Port ( input : in STD_LOGIC_VECTOR (2 downto 0);
output : out STD_LOGIC_VECTOR (1 downto 0));
end component;
-- SIGNAL
signal shift_control : std_logic_vector (1 downto 0);
begin
logic_device : shiftcontrollogic port map (G, shift_control);
-- instantiate an n-bit shift_rotate device with generic value "n"
-- mapped to a bit-width of 4. Note that the second data input is
-- connected directly to ground by using the 4-bit value "0000".
shift_device : nBitShiftRotateM generic map (4) port map (Data_In, "0000", G(0), G(1), G(0), G(1), shift_control, Output);
end Behavioral;
-- G2 G1 G0
-- 0 0 0 gets input no change
-- 0 0 1 shift input right
-- 0 1 0 shift input to the right and introduce a 0
-- 0 1 1 shift input to the right and introduce a 1
-- 1 0 0 gets input no change
-- 1 0 1 shift input
-- 1 1 0 shift input to the left and introduce a 0
-- 1 1 1 shift input to the left and introduce a 1 Test bench code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY four_bit_shifter_tb_vhd IS
END four_bit_shifter_tb_vhd;
ARCHITECTURE behavior OF four_bit_shifter_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT four_bit_shifter
PORT(
Data_In : IN std_logic_vector(3 downto 0);
G : IN std_logic_vector(2 downto 0);
Output : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL Data_In : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL G : std_logic_vector(2 downto 0) := (others=>'0');
--Outputs
SIGNAL Output : std_logic_vector(3 downto 0);
BEGIN
-- *** Comments on how this test bench works *** --
-- function table for the ALU with example inputs and expected outputs:
-- Function G Data_In : Output
------------------------------------:----------
-- Pass 000 0101 : 0101
-- Rotate left 001 0101 : 1010
-- Shift Left (0) 010 1111 : 1110
-- Shift Left (1) 011 0000 : 0001
-- Pass 100 1010 : 1010
-- Rotate right 101 1010 : 0101
-- Shift right (0) 110 1111 : 0111
-- Shift right (1) 111 0000 : 1000
-- Test bench should check each of these examples
-- ********************************************** --
-- Instantiate the Unit Under Test (UUT)
uut: four_bit_shifter PORT MAP(
Data_In => Data_In,
G => G,
Output => Output
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
G <= "000"; -- test Pass
Data_In <= "0101";
wait for 100 ns;
G <= "001"; -- test rotate left
Data_In <= "0101";
wait for 100 ns;
G <= "010"; -- test shift left (insert 0)
Data_In <= "1111";
wait for 100 ns;
G <= "011"; -- test shift left (insert 1)
Data_In <= "0000";
wait for 100 ns;
G <= "100"; -- test Pass
Data_In <= "1010";
wait for 100 ns;
G <= "101"; -- test rotate right
Data_In <= "1010";
wait for 100 ns;
G <= "110"; -- test shift right (insert 0)
Data_In <= "1111";
wait for 100 ns;
G <= "111"; -- test shift right (insert 1)
Data_In <= "0000";
wait for 100 ns;
-- Place stimulus here
wait; -- will wait forever
END PROCESS;
END; Component ( Shift control logic ) code in the description of the video
Component ( 4 bit shifter rotator ) code in the description of the video
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