This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.
The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:
Lab Sheets:
http://viahold.com/y37
Lab guide
http://cogismith.com/1OwP
The complete video tutorial at:
https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4
The design in this lab covers the basics of microcontrolller structural design
Intended Controlled datapath design design:
Datapath and controller internals:
Parts working on now (ALU):
VHDL Code:
Test bench code:
Component ( 4 bit 2 input multiplexer ) code in the video description
Component ( 4 bit Arithmetic Unit ) code in the video description
Component ( 4 bit Logic unit ) code in the video description
The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:
Lab Sheets:
http://viahold.com/y37
Lab guide
http://cogismith.com/1OwP
The complete video tutorial at:
https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4
The design in this lab covers the basics of microcontrolller structural design
Intended Controlled datapath design design:
Datapath and controller internals:
Parts working on now (ALU):
This is another components which will be used to construct the datapath. Refer to the lab sheets:
VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ENTITY
entity four_bit_alu is
Port ( InA : in std_logic_vector(3 downto 0);
InB : in std_logic_vector(3 downto 0);
F : in std_logic_vector(2 downto 0);
Output : out std_logic_vector(3 downto 0);
C_out : out std_logic);
end four_bit_alu;
-- ARCHITECHTURE
architecture Behavioral of four_bit_alu is
component four_bit_arithmetic_unit
Port ( InA : in STD_LOGIC_VECTOR (3 downto 0);
InB : in STD_LOGIC_VECTOR (3 downto 0);
Control : in STD_LOGIC_VECTOR (1 downto 0);
Sum : out STD_LOGIC_VECTOR (3 downto 0);
C_out : out STD_LOGIC);
end component;
component nbitlogicunit
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
control : in STD_LOGIC_VECTOR (1 downto 0);
output : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;
-- COMPONENTS:
component nbittwoinputmux
generic(n:positive:=4);
Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);
InB : in STD_LOGIC_VECTOR (n-1 downto 0);
Control : in STD_LOGIC;
Output : out STD_LOGIC_VECTOR (n-1 downto 0));
end component;
-- SIGNALS
signal arith_to_mux, logic_to_mux : std_logic_vector (3 downto 0);
begin
-- INSTANCES
-- instantiate the arithemetic unit:
arith : four_bit_arithmetic_unit port map (InA, InB, F(1 downto 0), arith_to_mux, C_out);
-- instantiate the logic unit with a bit-width of 4 (map generic value "n" to 4)
logic : nbitlogicunit port map (InA, InB, F(1 downto 0), logic_to_mux);
-- instantiate the mux with a bit-width of 4 (map generic value "n" to 4)
mux : nbittwoinputmux port map (logic_to_mux,arith_to_mux, F(2), output);
end Behavioral; Test bench code:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY four_bit_alu_tb_vhd IS
END four_bit_alu_tb_vhd;
ARCHITECTURE behavior OF four_bit_alu_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT four_bit_alu
PORT(
InA : IN std_logic_vector(3 downto 0);
InB : IN std_logic_vector(3 downto 0);
F : IN std_logic_vector(2 downto 0);
Output : OUT std_logic_vector(3 downto 0);
C_out : OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL InA : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL InB : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL F : std_logic_vector(2 downto 0) := (others=>'0');
--Outputs
SIGNAL Output : std_logic_vector(3 downto 0);
SIGNAL C_out : std_logic;
BEGIN
-- *** Comments on how this test bench works *** --
-- function table for the ALU with example inputs and expected outputs:
-- Function F InA InB : Output C_out
------------------------------:------------------
-- NOT A 000 0101 XXXX : 1010 X
-- A AND B 001 0011 0101 : 0001 X
-- A XOR B 010 0011 0101 : 0110 X
-- A OR B 011 0011 0101 : 0111 X
-- Inc A 100 0000 XXXX : 0001 0
-- A + B 101 0001 1111 : 0000 1
-- Dec A 110 0000 XXXX : 1111 1
-- A - B 111 1111 0001 : 1110 0
-- (X = "don't care")
-- Test bench should check each of these examples
-- ********************************************** --
-- Instantiate the Unit Under Test (UUT)
uut: four_bit_alu PORT MAP(
InA => InA,
InB => InB,
F => F,
Output => Output,
C_out => C_out
);
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
F <= "000"; -- test NOT A
InA <= "0101";
wait for 100 ns;
F <= "001"; -- test A AND B
InA <= "0011";
InB <= "0101";
wait for 100 ns;
F <= "010"; -- test A XOR B
InA <= "0011";
InB <= "0101";
wait for 100 ns;
F <= "011"; -- test A OR B
InA <= "0011";
InB <= "0101";
wait for 100 ns;
F <= "100"; -- test Inc A
InA <= "0000";
wait for 100 ns;
F <= "101"; -- test A + B
InA <= "0001";
InB <= "1111";
wait for 100 ns;
F <= "110"; -- test Dec A
InA <= "0000";
InB <= "0000";
wait for 100 ns;
F <= "111"; -- test A - B
InA <= "1111";
InB <= "0001";
wait; -- will wait forever
END PROCESS;
END; Component ( 4 bit 2 input multiplexer ) code in the video description
Component ( 4 bit Arithmetic Unit ) code in the video description
Component ( 4 bit Logic unit ) code in the video description
Gracias por el aporte! :D
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