VHDL 4 bit adder substractor structural design code test in circuit and test bench ISE design suite Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now (ALU):

This is another components which will be used to construct the datapath. Refer to the lab sheets:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity addersubstractor is  
 generic(n:positive:=4);  
   Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);  
       InB : in STD_LOGIC_VECTOR (n-1 downto 0);  
       control : in STD_LOGIC;  
       sum : out STD_LOGIC_VECTOR (n-1 downto 0);  
       cout : out STD_LOGIC);  
 end addersubstractor;  
 architecture Behavioral of addersubstractor is  
           component nbit_xor_contol is  
           Generic ( n : positive := 4 );  
                 Port ( Input : in std_logic_vector(n-1 downto 0);  
                           control : in std_logic;  
                           Output : out std_logic_vector(n-1 downto 0));  
           end component;  
           component fourbitlacadder   
           generic(n:positive:=4);  
                 Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);  
                           InB : in STD_LOGIC_VECTOR (n-1 downto 0);  
                           cin : in STD_LOGIC;  
                           sum : out STD_LOGIC_VECTOR (n-1 downto 0);  
                           cout : out STD_LOGIC);  
           end component;  
 signal xorcontroltolacadder:std_logic_vector(n-1 downto 0);  
 begin  
 A: nbit_xor_contol port map(InB,control,xorcontroltolacadder);  
 B: fourbitlacadder port map(InA,xorcontroltolacadder,control,sum,cout);  
 end Behavioral;  

Test bench code:

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY fourbitaddersubstractortestbench IS  
 END fourbitaddersubstractortestbench;  
 ARCHITECTURE behavior OF fourbitaddersubstractortestbench IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT addersubstractor  
   PORT(  
      InA : IN std_logic_vector(3 downto 0);  
      InB : IN std_logic_vector(3 downto 0);  
      control : IN std_logic;  
      sum : OUT std_logic_vector(3 downto 0);  
      cout : OUT std_logic  
     );  
   END COMPONENT;  
   --Inputs  
   signal InA : std_logic_vector(3 downto 0) := (others => '0');  
   signal InB : std_logic_vector(3 downto 0) := (others => '0');  
   signal control : std_logic := '0';  
       --Outputs  
   signal sum : std_logic_vector(3 downto 0);  
   signal cout : std_logic;  
   -- No clocks detected in port list. Replace <clock> below with   
   -- appropriate port name   
   constant <clock>_period : time := 10 ns;  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: addersubstractor PORT MAP (  
      InA => InA,  
      InB => InB,  
      control => control,  
      sum => sum,  
      cout => cout  
     );  
   -- Clock process definitions  
   -- Stimulus process  
   stim_proc: process  
   begin            
    -- hold reset state for 100 ns.  
    wait for 100 ns;       
    InA <= "0010";  --Addition  
            InB <= "0011";  
           control <= '0';  
           wait for 100 ns;       
    InA <= "0011";   -- Substractions  
           InB <= "0010";  
           control <= '1';  
    -- insert stimulus here   
    wait;  
   end process;  
 END;  

Component ( nbit xor control ) code in the video description

Component ( nbit LAC look ahead carry adder ) code in the video description