VHDL D flip flop with asyncronous reset preset code test in circuit and test bench ISE design suite Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

This is another components which will be used in the design. Refer to the lab sheets (Lab 3):

VHDL code:

 library IEEE;  
 use IEEE.std_logic_1164.all;  
 entity D_flipflop is  
 port (d, clk, reset, preset : in std_logic;  
           q,qnot: out std_logic);  
 end D_flipflop;  
 architecture behave of D_flipflop is  
 begin  
                process (clk, reset, preset) begin  
                          if (reset = '1') then  
                          q <= '0';  
                          qnot<='1';  
                          elsif (preset = '1') then  
                          q <= '1';  
                          qnot<='0';  
                          elsif (clk'event and clk = '1') then  
                          q <= d;  
                          qnot<= not d;  
                          end if;  
                end process;  
 end behave;  

Test bench code:

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY d_flipflop_test IS  
 END d_flipflop_test;  
 ARCHITECTURE behavior OF d_flipflop_test IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT D_flipflop  
   PORT(  
      d : IN std_logic;  
      reset : IN std_logic;  
      preset : IN std_logic;  
      clk : IN std_logic;  
      q : OUT std_logic;  
      qnot : OUT std_logic  
     );  
   END COMPONENT;  
   --Inputs  
   signal d : std_logic := '0';  
   signal reset : std_logic := '0';  
   signal preset : std_logic := '0';  
   signal clk : std_logic := '0';  
       --Outputs  
   signal q : std_logic;  
   signal qnot : std_logic;  
   -- Clock period definitions  
   constant clk_period : time := 10 ns;  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: D_flipflop PORT MAP (  
      d => d,  
      reset => reset,  
      preset => preset,  
      clk => clk,  
      q => q,  
      qnot => qnot  
     );  
 -- SET CLOCK PERIOD  
      clk <= not clk after 50 ns; -- period = 100ns  
      tb : PROCESS  
      BEGIN  
           -- Wait 100 ns for global reset to finish  
           wait for 100 ns;  
           -- both outputs start undefined 'U'  
           reset <= '1';  
           d <= '1';  
           -- this sets Q to '0' and Q_bar to '1'  
           -- note that while reset is asserted, the flip-flop  
           -- does not react to the clock signal  
           wait for 120ns;  
           d <= '0';  
           -- this sets Q to '0' and Q_bar to '1'  
           -- note that while reset is asserted, the flip-flop  
           -- does not react to the clock signal   
           wait for 120ns;  
           reset <= '0';  
           -- after reset changes to 0, the Q output value will toggle   
           -- on each rising clock edge.   
           wait for 100 ns;  
           -- both outputs start undefined 'U'  
           preset <= '1';  
           d <= '1';  
           -- this sets Q to '0' and Q_bar to '1'  
           -- note that while reset is asserted, the flip-flop  
           -- does not react to the clock signal  
           wait for 120ns;  
           d <= '0';  
           -- this sets Q to '0' and Q_bar to '1'  
           -- note that while reset is asserted, the flip-flop  
           -- does not react to the clock signal  
           wait for 120ns;  
           preset <= '0';  
           wait for 100 ns;  
           -- both outputs start undefined 'U'  
           d <= '1';  
           -- this sets Q to '0' and Q_bar to '1'  
           -- note that while reset is asserted, the flip-flop  
           -- does not react to the clock signal  
           wait for 120ns;  
           d <= '0';  
    wait;  
   end process;  
 END;