VHDL 1 bit full adder code test in circuit and test bench

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:
http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

This tutorial uses components to understand the basics of microcontroller design.

Intended design:

Datapath and controller internals:

     

Parts working on now:

Constructing the alu:

For constructing the ALU we need an adder, the adder is formed by two half adders and the half adder is formed with gates. Refer to the lab sheets:  

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity fulladder is  
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       cin : in STD_LOGIC;  
       sum : out STD_LOGIC;  
       cout : out STD_LOGIC);  
 end fulladder;  
 architecture Behavioral of fulladder is  
 signal xor1,and_1,and_2:std_logic;  
 begin  
 xor<= a xor b;  
 sum<= xor1 xor cin;  
 and_1<= xor1 and cin;  
 and_2<= a and b;  
 cout<= and_1 or and_2;  
 end Behavioral;  
 --      INPUTS           OUTPUTS  
 --A       B       CIN       COUT      S  
 --0      1 0       0       0       0  
 --0       0       1       0       1  
 --0       1       0       0       1  
 --0       1       1       1       0  
 --1       0       0       0       1  
 --1       0       1       1       0  
 --1       1       0       1       0  
 --1       1       1       1       1  

Testbench

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY FULLADDERTest IS  
 END FULLADDERTest;  
 ARCHITECTURE behavior OF FULLADDERTest IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT fulladder  
   PORT(  
      a : IN std_logic;  
      b : IN std_logic;  
      cin : IN std_logic;  
      sum : OUT std_logic;  
      cout : OUT std_logic  
     );  
   END COMPONENT;  
   --Inputs  
   signal a : std_logic := '0';  
   signal b : std_logic := '0';  
   signal cin : std_logic := '0';  
       --Outputs  
   signal sum : std_logic;  
   signal cout : std_logic;  
   -- No clocks detected in port list. Replace <clock> below with   
   -- appropriate port name   
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: fulladder PORT MAP (  
      a => a,  
      b => b,  
      cin => cin,  
      sum => sum,  
      cout => cout  
     );  
   -- Stimulus process -- test for all possible inputs of full adder - 8 combinations  
   stim_proc: process  
  begin            
  wait for 100 ns; -- wait for global reset  
  a <= '0';  
  b <= '0';   
  cin <= '0';  
  wait for 100 ns;  
  a <= '0';   
  b <= '0';   
  cin <= '1';  
  wait for 100 ns;  
  a <= '0';   
  b <= '1';   
  cin <= '0';  
  wait for 100 ns;  
  a <= '0';   
  b <= '1';   
  cin <= '1';  
  wait for 100 ns;   
  a <= '1';  
  b <= '0';   
  cin <= '0';  
  wait for 100 ns;  
  a <= '1';   
  b <= '0';   
  cin <= '1';  
  wait for 100 ns;  
  a <= '1';   
  b <= '1';   
  cin <= '0';  
  wait for 100 ns;  
  a <= '1';   
  b <= '1';   
  cin <= '1';  
    wait;  
   end process;  
 END;