VHDL 4 bit Arithmetic Unit structural design code test in circuit and test bench ISE design suite Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now (ALU):

This is another components which will be used to construct the datapath. Refer to the lab sheets:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity four_bit_arithmetic_unit is  
   Port ( InA : in STD_LOGIC_VECTOR (3 downto 0);  
       InB : in STD_LOGIC_VECTOR (3 downto 0);  
       Control : in STD_LOGIC_VECTOR (1 downto 0);  
       Sum : out STD_LOGIC_VECTOR (3 downto 0);  
       C_out : out STD_LOGIC);  
 end four_bit_arithmetic_unit;  
 architecture Behavioral of four_bit_arithmetic_unit is  
 Component nbittwoinputmux   
 generic(n:positive:=4);   
   Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);  
       InB : in STD_LOGIC_VECTOR (n-1 downto 0);  
       Control : in STD_LOGIC;  
       Output : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 component addersubstractor   
 generic(n:positive:=4);  
   Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);  
       InB : in STD_LOGIC_VECTOR (n-1 downto 0);  
       control : in STD_LOGIC;  
       sum : out STD_LOGIC_VECTOR (n-1 downto 0);  
       cout : out STD_LOGIC);  
 end component;  
 signal muxtoadder:std_logic_vector(3 downto 0);  
 begin  
 A: nbittwoinputmux port map("0001",InB,Control(0),muxtoadder);  
 B: addersubstractor port map(InA,muxtoadder,Control(1),Sum,C_out);  
 end Behavioral;  
 --  control   operation  
 --  C1 C0     
 --  0 0    ADD 1 to input A  
 --  0 1    ADD input A + input B  
 --  1 0    SUB 1 to input A  
 --  1 1    SUB input A - input B  

Test bech code:

 library ieee;  
 use ieee.std_logic_1164.all;  
 entity four_bit_arithmetic_unit_tb is  
 end four_bit_arithmetic_unit_tb;  
 architecture behavior of four_bit_arithmetic_unit_tb is   
   component four_bit_arithmetic_unit  
   port(  
      InA : in std_logic_vector(3 downto 0);  
      InB : in std_logic_vector(3 downto 0);  
      control : in std_logic_vector(1 downto 0);  
      sum : out std_logic_vector(3 downto 0);  
      c_out : out std_logic  
     );  
   end component;  
   --inputs  
   signal InA : std_logic_vector(3 downto 0) := (others => '0');  
   signal InB : std_logic_vector(3 downto 0) := (others => '0');  
   signal control : std_logic_vector(1 downto 0) := (others => '0');  
       --outputs  
   signal sum : std_logic_vector(3 downto 0);  
   signal c_out : std_logic;  
 begin  
   uut: four_bit_arithmetic_unit port map (   
      InA => InA,  
      InB => InB,  
      control => control,  
      sum => sum,  
      c_out => c_out  
     );  
   -- Stimulus process  
   stim_proc: process  
   begin            
    -- hold reset state for 100 ns.  
    wait for 100 ns;       
           Control <= "00";           -- test Inc A  
           InA <= "0000";  
           wait for 100 ns;  
           Control <= "01";           -- test A + B  
           InA <= "0001";  
           InB <= "1111";  
           wait for 100 ns;  
           Control<= "10";           -- test Dec A  
           InA <= "1110";  
           InB <= "0000";  
           wait for 100 ns;  
           Control <= "11";           -- test A - B  
           InA <= "1111";  
           InB <= "0001";  
    wait;                 
   end process;  
 end;  

Component ( 4 bit 2 input multiplexer ) code in the video description

Component ( 4 bit adder substractor ) code in the video description