VHDL 3 input nor gate code ISE design suite Xilinx SPARTAN 3

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:
http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP


Intended design:

Datapath and controller internals:

   

Parts working on now:

Constructing the alu:

For constructing the ALU we need an adder, the adder is formed by two half adders and the half adder is formed with gates. Refer to the lab sheets:  

VHDL code:

--------------------------------------------------------------------------------

THREE INPUT NOR GATE MODULE

--------------------------------------------------------------------------------  
 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity threeinputnorgate is  
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       c : in STD_LOGIC;  
       f : out STD_LOGIC);  
 end threeinputnorgate;  
 architecture Behavioral of threeinputnorgate is  
 signal xory,xorz:std_logic;  
 begin  
 xory<= a or b;  
 xorz<= xory or c;  
 f<= not xorz;  
 end Behavioral;  

TESTBENCH

 -- Notes:   
 -- This testbench has been automatically generated using types std_logic and  
 -- std_logic_vector for the ports of the unit under test. Xilinx recommends   
 -- that these types always be used for the top-level I/O of a design in order   
 -- to guarantee that the testbench will bind correctly to the post-implementation   
 -- simulation model.  
 --------------------------------------------------------------------------------  
 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 USE ieee.std_logic_unsigned.all;  
 USE ieee.numeric_std.ALL;  
 ENTITY four_bit_lac_tb_vhd IS  
 END four_bit_lac_tb_vhd;  
 ARCHITECTURE behavior OF four_bit_lac_tb_vhd IS   
      -- Component Declaration for the Unit Under Test (UUT)  
      COMPONENT four_bit_lac  
      PORT(  
           InA : IN std_logic_vector(3 downto 0);  
           InB : IN std_logic_vector(3 downto 0);  
           C_In : IN std_logic;       
           C_terms : OUT std_logic_vector(3 downto 0)  
           );  
      END COMPONENT;  
      --Inputs  
      SIGNAL C_In : std_logic := '0';  
      SIGNAL InA : std_logic_vector(3 downto 0) := (others=>'0');  
      SIGNAL InB : std_logic_vector(3 downto 0) := (others=>'0');  
      --Outputs  
      SIGNAL C_terms : std_logic_vector(3 downto 0);  
 BEGIN  
 -- *** Comments on how this test bench works *** --            
 -- The LAC generates the carry terms that we would   
 -- expect to see on the outputs of each full adder  
 -- in a 4-bit ripple adder. This test bench checks   
 -- that the correct carries are generated using the   
 -- following bit patterns:  
 --      InA     InB     :      C_terms   
 --  0000     0000     :     0000  
 --          0001 0001 : 0010  
 --          0010 0010 : 0100  
 --          0100 0100 : 1000  
 --  0001     1111     :     1110  
 -- ********************************************** --  
      -- Instantiate the Unit Under Test (UUT)  
      uut: four_bit_lac PORT MAP(  
           InA => InA,  
           InB => InB,  
           C_In => C_In,  
           C_terms => C_terms  
      );  
      tb : PROCESS  
      BEGIN  
           -- Wait 100 ns for global reset to finish  
           wait for 100 ns;  
           InA <= "0001";  
           InB <= "0001";  
           wait for 100 ns;  
           InA <= "0010";  
           InB <= "0010";  
           wait for 100 ns;  
           InA <= "0100";  
           InB <= "0100";  
           wait for 100 ns;  
           InA <= "0001";  
           InB <= "1111";  
           wait; -- will wait forever  
      END PROCESS;  
 END;