VHDL 4 bit xor gate control using components structural design code test bench and test on development board ISE design suite Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:
http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP


Intended design:

Datapath and controller internals:

     

Parts working on now:

Constructing the alu:

For constructing the ALU we need an adder, the adder is formed by two half adders and the half adder is formed with gates. Refer to the lab sheets:  

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity nbitxorcontrol is  
 generic(n:positive:=4);  
   Port ( Input : in STD_LOGIC_VECTOR (n-1 downto 0);  
       Control : in STD_LOGIC;  
       Output : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end nbitxorcontrol;  
 architecture Behavioral of nbitxorcontrol is  
 component xorgate  
 Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       f : out STD_LOGIC);  
 end component;  
 begin  
 inst: for i in n-1 downto 0 generate  
 nmuxcontrol: orgate port map(Input(i),control, Output(i));  
 end generate;  
 end Behavioral;  

Or gate Component code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity xorgate is  
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       f : out STD_LOGIC);  
 end xorgate;  
 architecture Behavioral of xorgate is  
 begin  
 f<= a xor b;  
 end Behavioral;  
 --a  b f  
 --0     0     0  
 --0     1     1  
 --1     0     1  
 --1     1     0