VHDL 1 bit tri state buffer code test in circuit and test bench ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

This is another components which will be used to construct the datapath. Refer to the lab sheets(lab 3) :

VHDL code

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 -- ********* COMMENTS ON HOW THIS DEVICE DESIGN WORKS ******************  
 ----  
 -- ENTITY   
 -- the entity declaration defines the interface of "tristate_buffer"   
 --  
 -- ARCHITECTURE   
 -- architecture describes the internal structure of the device   
 --  
 -- PROCESS  
 -- This device uses a VHDL "process" to determine its output value.  
 -- The process watches the values of "Input" and "enable" and evaluates   
 -- the output value according to the IF statement when an input changes.   
 --  
 -- *********************************************************************  
 -- ENTITY  
 entity tri_buff is  
   Port ( Input : in std_logic;  
       enable : in std_logic;  
       Output : out std_logic);  
 end tri_buff;  
 -- ARCHITECTURE  
 architecture Behavioral of tri_buff is  
 begin  
                     -- PROCESS  
                     process(input, enable)  
                          begin  
                               -- IF statement  
                               if enable = '1' then  
                                    output <= input after 7 ns;  
                               else  
                                    output <= 'Z' after 7 ns;  
                               end if;  
                     end process;  
 end Behavioral;  

Test bench

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 USE ieee.std_logic_unsigned.all;  
 USE ieee.numeric_std.ALL;  
 ENTITY tri_buff_tb_vhd IS  
 END tri_buff_tb_vhd;  
 ARCHITECTURE behavior OF tri_buff_tb_vhd IS   
      -- Component Declaration for the Unit Under Test (UUT)  
      COMPONENT tri_buff  
      PORT(  
           Input : IN std_logic;  
           enable : IN std_logic;       
           Output : OUT std_logic  
           );  
      END COMPONENT;  
      --Inputs  
      SIGNAL Input : std_logic := '0';  
      SIGNAL enable : std_logic := '0';  
      --Outputs  
      SIGNAL Output : std_logic;  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
      uut: tri_buff PORT MAP(  
           Input => Input,  
           enable => enable,  
           Output => Output  
      );  
      tb : PROCESS  
      BEGIN  
 -- *** Comments on how this test bench works *** --            
           -- truth table for a tristate buffer:  
           -- enable input : output  
           -----------------:------------  
           --          0            0  :     Hi-Z    
        --          0            1  :     Hi-Z    
        --          1            0  :      0    
        --          1            1  :      1    
 -- ********************************************** --  
           -- Wait 100 ns for global reset to finish  
           wait for 100 ns;  
           -- test Hi-Z output (i.e. output disabled - high impedance)  
           input <= '0';  
           enable <= '0';  
           wait for 100 ns;  
           input <= '1';  
           -- test normal output (i.e. output enabled)  
           wait for 100 ns;  
           input <= '0';  
           enable <= '1';  
           wait for 100 ns;  
           input <= '1';  
           wait; -- will wait forever  
      END PROCESS;  
 END;