VHDL 1 bit logic fuction slice structural design , test on circuit and test bench ISE design suite Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

 

Parts working on now (ALU):

This is another components which will be used to construct the datapath. Refer to the lab sheets:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity bitsliceLogicslice is  
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       control : in STD_LOGIC_VECTOR (1 downto 0);  
       output : out STD_LOGIC);  
 end bitsliceLogicslice;  
 architecture Behavioral of bitsliceLogicslice is  
 component inverter   
   Port ( a : in STD_LOGIC;  
       f : out STD_LOGIC);  
 end component;  
 component andgate  
 Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       f : out STD_LOGIC);  
 end component;  
 component orgate  
 Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       f : out STD_LOGIC);  
 end component;  
 component xorgate  
 Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       f : out STD_LOGIC);  
 end component;  
 component fourinputmux   
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       c : in STD_LOGIC;  
       d : in STD_LOGIC;  
       control : in STD_LOGIC_VECTOR (1 downto 0);  
       output : out STD_LOGIC);  
 end component;  
 signal invertertomux,andtomux,xortomux,ortomux:std_logic;  
 begin  
 A1: inverter port map (a,invertertomux);  
 B1: andgate port map (a,b,andtomux);  
 C1: xorgate port map(a,b,xortomux);  
 D1: orgate port map(a,b,ortomux);  
 E1: fourinputmux port map (invertertomux,andtomux,xortomux,ortomux,control,output);  
 end Behavioral;  

Test bench code:

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY bit_slice_test IS  
 END bit_slice_test;  
 ARCHITECTURE behavior OF bit_slice_test IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT bitsliceLogicslice  
   PORT(  
      a : IN std_logic;  
      b : IN std_logic;  
      control : IN std_logic_vector (3 downto 0);  
      output : OUT std_logic  
     );  
   END COMPONENT;  
   --Inputs  
   signal a : std_logic := '0';  
   signal b : std_logic := '0';  
   SIGNAL control : std_logic_vector(1 downto 0) := (others=>'0');  
       --Outputs  
   signal output : std_logic;  
   -- No clocks detected in port list. Replace <clock> below with   
   -- appropriate port name   
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: bitsliceLogicslice PORT MAP (  
      a => a,  
      b => b,  
      control => control,  
      output => output  
     );  
   -- Clock process definitions  
   -- Stimulus process  
   stim_proc: process  
   begin            
    -- hold reset state for 100 ns.  
  wait for 100 ns; -- wait for global reset  
  a <= '0'; -- check not gate input 0 output 1  
  control <= "00"; -- check 0 nand 0 = 1  
  wait for 100 ns; -- wait for global reset  
  a <= '1'; --and gate  
  b <= '1';  
  control <= "01"; -- check 0 and 0 = 1  
  wait for 100 ns;  
  a <= '1'; -- xor gate  
  b <= '0';  
  control <= "10"; -- check 0 nand 0 = 1  
  wait for 100 ns; -- wait for global reset  
 a <= '1'; -- or gate  
  b <= '1';  
  control <= "11"; -- check 0 nand 0 = 1  
  wait; -- end of test: wait for ever  
    -- insert stimulus here   
    wait;  
   end process;  
 END;  

Component ( 1 bit four input multiplexer ) code in the video description

 VHDL Component ( inverter , not gate ) code in the video description

VHDL Component ( and gate ) code in the video description

 VHDL Component ( xgate ) code in the video description

 VHDL Component ( xgate ) code in the video description