VHDL nbit - 4 bit register with load hold and state buffer output control code test in circuit and test bench ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

This is another components which will be used to construct the datapath. Refer to the lab sheets(lab 3) :

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 ------------------------------------------------------------------------  
 entity nbitregloadholdcontroltristate is  
 generic(n:positive:=4);  
   Port ( dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       loadhold : in STD_LOGIC;  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       outputenable : in STD_LOGIC;  
       qoutputs : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end nbitregloadholdcontroltristate;  
 ------------------------------------------------------------------------  
 architecture Behavioral of nbitregloadholdcontroltristate is  
 component nbitregloadhold   
 generic(n:positive:=4);  
   Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       loadhold : in STD_LOGIC;  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       preset : in STD_LOGIC;  
       qoutputs : inout STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 component nbittristatebuffer   
 generic(n:positive:=4);  
   Port ( datain : in STD_LOGIC_VECTOR (n-1 downto 0);  
       enable : in STD_LOGIC;  
       output : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 signal tobuffer:std_logic_vector(n-1 downto 0);---  
 ------------------------------------------------------------------------  
 begin  
 A: nbitregloadhold port map(dinputs,loadhold,CLK,reset,'0',tobuffer);  
 B: nbittristatebuffer port map(tobuffer, outputenable,qoutputs);  
 end Behavioral;  

TEST bench code:

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY nbitregloadholdtristatebuffertest IS  
 END nbitregloadholdtristatebuffertest;  
 ARCHITECTURE behavior OF nbitregloadholdtristatebuffertest IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT nbitregloadholdcontroltristate  
   PORT(  
      dinputs : IN std_logic_vector(3 downto 0);  
      loadhold : IN std_logic;  
      CLK : IN std_logic;  
      reset : IN std_logic;  
      outputenable : IN std_logic;  
      qoutputs : OUT std_logic_vector(3 downto 0)  
     );  
   END COMPONENT;  
   --Inputs  
   signal dinputs : std_logic_vector(3 downto 0) := (others => '0');  
   signal loadhold : std_logic := '0';  
   signal CLK : std_logic := '0';  
   signal reset : std_logic := '0';  
   signal outputenable : std_logic := '0';  
       --Outputs  
   signal qoutputs : std_logic_vector(3 downto 0);  
   -- Clock period definitions  
   constant CLK_period : time := 10 ns;  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: nbitregloadholdcontroltristate PORT MAP (  
      dinputs => dinputs,  
      loadhold => loadhold,  
      CLK => CLK,  
      reset => reset,  
      outputenable => outputenable,  
      qoutputs => qoutputs  
     );  
  clk_process :process  
   begin  
           clk <= '0';  
           wait for clk_period/2;  
           clk <= '1';  
           wait for clk_period/2;  
   end process;  
   -- Stimulus process  
   stim_proc: process  
   begin            
    -- hold reset state for 100 ns.  
    wait for 100 ns;       
            wait for 100 ns;       
 outputenable<='0';  
    dinputs <= "1001" ;  
              wait for 100 ns;       
      outputenable<='1';   
                loadhold <= '1';  
                             wait for 100 ns;       
              wait for 100 ns;        
      outputenable<='1';  
                loadhold <= '0';  
      wait for 100 ns;        
      outputenable<='0';  
                loadhold <= '0';  
              wait for 100 ns;        
      outputenable<='1';  
                loadhold <= '0';  
                     wait for 100 ns;       
                     reset <= '1';  
                     wait for 100 ns;        
                          reset <= '0';  
    wait for clk_period*10;  
    -- insert stimulus here   
    wait;  
   end process;  
 END;  

Component ( nbit 4 bit register with load and hold ) code in the video description

Component( nbit 4 bit tri state buffer ) code in the video description