VHDL 4 bit linear feedback register code test in circuit ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

This is another component which will be used in the controlled datapath. Refer to the lab sheets(lab 3) :

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity bit4linearfeedbackshiftreg is  
 ------------input outputs--------------------------  
  generic (n : positive := 4);  
 port(CLK: in std_logic;  
           reset: in std_logic;   
           preset: in std_logic;  
           qoutputs:inout std_logic_vector(n-1 downto 0));  
 end bit4linearfeedbackshiftreg;  
 architecture Behavioral of bit4linearfeedbackshiftreg is  
 ----------------components-------------------------  
 component xorgate  
 Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       f : out STD_LOGIC);  
 end component;  
 component nbitserialparalelshiftreg  
  generic (n : positive := 4);  
   Port ( shift_in : in std_logic;  
       CLK : in std_logic;  
       reset : in std_logic;  
       preset : in std_logic;  
       Q_shift : out std_logic_vector(n-1 downto 0));  
 end component;  
  signal toreg: std_Logic;  
 begin  
 ----------------------port map------------------------  
 A: xorgate port map(qoutputs(n-1),qoutputs(n-2),toreg);  
 B: nbitserialparalelshiftreg port map(toreg,CLK,reset,preset,qoutputs);  
 end Behavioral;  

 Component ( xor gate ) code in the videos description

Component ( nbit serial to parallel shift register ) code in the video description

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE