VHDL nbit - 8 bit parallel load shift - serial to parallel shift register structural design code test in circuit ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Refer to the lab sheets:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity nbitshiftregparallelload is  
 generic(n:positive:=8);  
   Port ( shiftin : in STD_LOGIC;  
       dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       loadshift : in STD_LOGIC;  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       preset : in STD_LOGIC;  
       qoutputs : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end nbitshiftregparallelload;  
 architecture Behavioral of nbitshiftregparallelload is  
 component nbittwoinputmux   
 generic(n:positive:=8);  
   Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);  
       InB : in STD_LOGIC_VECTOR (n-1 downto 0);  
       Control : in STD_LOGIC;  
       Output : out STD_LOGIC_VECTOR (n-1 downto 0));   
 end component;  
 component nbitregister   
 generic(n:positive:=8);  
   Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       preset : in STD_LOGIC;  
       q : out STD_LOGIC_VECTOR (n-1 downto 0);  
       qnot : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 signal feedback:std_logic_vector(n downto 0);  
 signal muxToReg,dummy:std_logic_vector(n-1 downto 0);  
 begin  
 feedback(0) <= shiftin;  
 A: nbittwoinputmux port map(feedback(n-1 downto 0),dinputs, loadshift, muxToReg);  
 B: nbitregister port map(muxToReg,CLK, reset, preset, feedback(n downto 1), dummy);  
 qoutputs <= feedback(n downto 1);  
 end Behavioral;  

Component  ( nbit two input multiplexer ) code in the video description

Component ( n bit register ) coe in the video description

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