VHDL 4 bit synchronous up down counter structural design using components code plus test in circuit ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 ---- Uncomment the following library declaration if instantiating  
 ---- any Xilinx primitives in this code.  
 --library UNISIM;  
 --use UNISIM.VComponents.all;  
 entity bit4SynchronousUpDownCounter is  
 generic(n:positive:=4);  
   Port ( N_count : in STD_LOGIC_VECTOR (n-1 downto 0);  
       downUp : in STD_LOGIC;  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       Q_output : out STD_LOGIC_VECTOR (n-1 downto 0)  
       );  
 end bit4SynchronousUpDownCounter;  
 architecture Behavioral of bit4SynchronousUpDownCounter is  
 component addersubstractor   
 generic(n:positive:=4);  
   Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);  
       InB : in STD_LOGIC_VECTOR (n-1 downto 0);  
       control : in STD_LOGIC;  
       sum : out STD_LOGIC_VECTOR (n-1 downto 0);  
       cout : out STD_LOGIC);  
 end component;       
 component nbitregister   
 generic(n:positive:=4);  
   Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       preset : in STD_LOGIC;  
       q : out STD_LOGIC_VECTOR (n-1 downto 0);  
       qnot : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 signal nc2,sumToRegister,outputToInA:std_logic_vector(n-1 downto 0);       
 signal nc1:std_logic;       
 begin  
 Q_output<=outputToInA;  
 PartA: addersubstractor generic map(4) port map(outputToInA,N_count,downUp,sumToRegister,nc1);  
 PartB: nBitRegister generic map(4) port map(sumToRegister,clk,reset,'0',outputToInA,nc2);  
 Q_output<=outputToInA;  
 end Behavioral;  

Component ( adder substractor ) code in the video description

Component ( nbit - 4 bit register ) code in the video description

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE