electronics blog: VHDL 4 bit synchronous counter with next state logic structural design code plus test in circuit ISE Xilinx spartan 3

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

VHDL CODE:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 --------------------entity-------------------------------------  
 entity bit_sync_counter is  
           generic ( n : positive := 4);  
   Port ( CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       Q_outputs : inout STD_LOGIC_VECTOR (n-1 downto 0));  
 end bit_sync_counter;  
 ---------------------architecture----------------------------  
 architecture Behavioral of bit_sync_counter is  
 ----------------------components--------------------------------  
 component nbitregister is  
 generic(n:positive:=4);  
   Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       preset : in STD_LOGIC;  
       q : out STD_LOGIC_VECTOR (n-1 downto 0);  
       qnot : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 component next_state_logic   
           generic ( n : positive := 4);  
   Port ( Input : in STD_LOGIC_VECTOR ( n-1 downto 0);  
       Output : out STD_LOGIC_VECTOR ( n-1 downto 0));  
                 end component;  
 signal dummy, new_Output: STD_LOGIC_VECTOR (n-1 downto 0);  
 begin  
 ------------------------port map---------------------------------  
 NXt_State_it: next_state_logic port map (Q_outputs, new_Output);  
 N_bit_it: nbitregister port map (new_Output,clk, reset, '0', Q_outputs, dummy );  
 end Behavioral;

Test bench:

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY bit_sync_counter_test IS  
 END bit_sync_counter_test;  
 ARCHITECTURE behavior OF bit_sync_counter_test IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT bit_sync_counter  
   PORT(  
      CLK : IN std_logic;  
      reset : IN std_logic;  
      Q_outputs : INOUT std_logic_vector(3 downto 0)  
     );  
   END COMPONENT;  
   --Inputs  
   signal CLK : std_logic := '0';  
   signal reset : std_logic := '0';  
      --BiDirs  
   signal Q_outputs : std_logic_vector(3 downto 0);  
   -- Clock period definitions  
   constant CLK_period : time := 100 ns;  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: bit_sync_counter PORT MAP (  
      CLK => CLK,  
      reset => reset,  
      Q_outputs => Q_outputs  
     );  
   -- Clock process definitions  
   CLK_process :process  
   begin  
           CLK <= '0';  
           wait for CLK_period/2;  
           CLK <= '1';  
           wait for CLK_period/2;  
   end process;  
   -- Stimulus process  
   stim_proc: process  
   begin            
    -- hold reset state for 100 ns.  
    wait for 100 ns;       
 reset<= '1';     
     wait for 100 ns;       
 reset<= '0';     
     wait for 100 ns;       
   end process;  
 END;

Component ( 4 bit next state logic ) code in the video description