VHDL nbit ripple counter structural design code plus test in circuit ISE Xilinx spartan 3 development board

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

This is another component which will be used in the controlled datapath. Refer to the lab sheets(lab 3) :

VHDL code

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 entity n_bit_ripple_counter is  
       generic(n: positive:= 8);  
   Port ( CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       Q_outputs : inout STD_LOGIC_VECTOR (n-1 downto 0);  
       Q_bar_outputs : inout STD_LOGIC_VECTOR (n-1 downto 0));  
 end n_bit_ripple_counter;  
 architecture Behavioral of n_bit_ripple_counter is  
 component Tflipflopasynchronous  
  Port ( reset : in STD_LOGIC;  
       CLK : in STD_LOGIC;  
       q : inout STD_LOGIC;  
       qnot : inout STD_LOGIC);  
 end component;  
 signal tonextT:std_logic_vector(n-1 downto 0);  
 begin  
 --Q_bar_outputs<=tonextT;  
      inst : for i in n-1 downto 0 generate       
      if1: if i = 0 generate  
         T_it: Tflipflopasynchronous port map ( reset, CLK, Q_outputs(i),Q_bar_outputs(i)) ;  
      end generate;  
       if2:if i/=0 generate   
      T_it: Tflipflopasynchronous port map ( reset, Q_bar_outputs(i-1), Q_outputs(i),Q_bar_outputs(i)) ;  
      end generate;  
      end generate;  
 end Behavioral;  

Test bench :

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY n_bit_ripple_counter_test IS  
 END n_bit_ripple_counter_test;  
 ARCHITECTURE behavior OF n_bit_ripple_counter_test IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT n_bit_ripple_counter  
   PORT(  
      CLK : IN std_logic;  
      reset : IN std_logic;  
      Q_outputs : INOUT std_logic_vector(7 downto 0);  
      Q_bar_outputs : INOUT std_logic_vector(7 downto 0)  
     );  
   END COMPONENT;  
   --Inputs  
   signal CLK : std_logic := '0';  
   signal reset : std_logic := '0';  
      --BiDirs  
   signal Q_outputs : std_logic_vector(7 downto 0);  
   signal Q_bar_outputs : std_logic_vector(7 downto 0);  
   -- Clock period definitions  
   constant CLK_period : time := 10 ns;  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: n_bit_ripple_counter PORT MAP (  
      CLK => CLK,  
      reset => reset,  
      Q_outputs => Q_outputs,  
      Q_bar_outputs => Q_bar_outputs  
     );  
   -- Clock process definitions  
   CLK_process :process  
   begin  
           CLK <= '0';  
           wait for CLK_period/2;  
           CLK <= '1';  
           wait for CLK_period/2;  
   end process;  
   -- Stimulus process  
   stim_proc: process  
   begin            
    -- hold reset state for 100 ns.  
    wait for 100 ns;       
    wait for CLK_period*10;  
      wait for 100 ns;  
           -- both outputs start undefined 'U'  
           reset <= '1';  
           -- this sets Q to '0' and Q_bar to '1'  
           -- note that while reset is asserted, the flip-flop  
           -- does not react to the clock signal  
           wait for 120ns;  
           reset <= '0';  
           -- after reset changes to 0, the Q output value will toggle   
           -- on each rising clock edge.  
           wait for 100 ns;  
           reset <= '1';  
           wait for 120ns;  
           reset <= '0';  
                     wait for 100 ns;  
           reset <= '1';  
           wait for 120ns;  
           reset <= '0';  
                     wait for 100 ns;  
           reset <= '1';  
           wait for 120ns;  
           reset <= '0';  
                     wait for 100 ns;  
           reset <= '1';  
           wait for 120ns;  
           reset <= '0';  
                     wait for 100 ns;  
           reset <= '1';  
           wait for 120ns;  
           reset <= '0';  
                     wait for 100 ns;  
           reset <= '1';  
           wait for 120ns;  
           reset <= '0';  
    wait;  
   end process;  
 END;  

Component ( T flip flop ) code in the video description

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE