VHDL nbit - 8 bit modulo m counter with synchronous reset code plus test in circuit ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

note: to make it 8 bits just change the definitions for generic n to 8 bits (the components need to be changed as well)
VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 ----------------------------------------------------  
 -- Top level design  
 ----------------------------------------------------  
 entity syncModMCount is  
      Generic (n: positive:= 4);  
   Port ( input : in STD_LOGIC_VECTOR (n-1 downto 0);  
       countEnable : in STD_LOGIC;  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       Q_Out : out STD_LOGIC_VECTOR(n-1 downto 0));  
 end syncModMCount;  
 ----------------------------------------------------  
 -- Internal Architecture  
 ----------------------------------------------------  
 architecture Behavioral of syncModMCount is  
 --COMPONENT: 8-bit comparator  
 component bit8Comparator is  
   generic(n:positive:=4);  
       Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);  
       InB : in STD_LOGIC_VECTOR (n-1 downto 0);  
       Output : out STD_LOGIC);  
 end component;  
 --END COMPONENT: 8-bit comparator  
 --COMPONENT: nBitSyncCountPL  
 component nbitsynchronouscounterwithparallelload is  
 generic(n:positive:=4);  
   Port ( dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       loadcount : in STD_LOGIC;  
       countenable : in STD_LOGIC;  
       clk : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       qoutputs : inout STD_LOGIC_VECTOR (n-1 downto 0)  
                 );  
 end component;  
 --END COMPONENT: nBitSyncCountPL  
 --SIGNALS  
 signal counterToComparator: std_logic_vector(n-1 downto 0);  
 signal comparatorToCounter: std_logic;  
 begin  
      newComparator: bit8Comparator port map (counterToComparator, input, comparatorToCounter);  
      newCounter: nbitsynchronouscounterwithparallelload port map ("0000", comparatorToCounter, countEnable, CLK, reset, counterToComparator);  
      Q_Out <= counterToComparator;  
 end Behavioral;  

Components ( 8 bit comparator ) code in the video description

Components ( 8 bit synchronous counter with parallel load ) code in the video description

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE