VHDL nbit - 8 bit serial to parallel shift register code test in circuit and test bench ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

This is another components which will be used to construct the datapath. Refer to the lab sheets(lab 3) :

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 -- ENTITY  
 entity nbitserialparalelshiftreg is  
       generic (n : positive := 8);  
   Port ( shift_in : in std_logic;  
       CLK : in std_logic;  
       reset : in std_logic;  
       preset : in std_logic;  
       Q_shift : out std_logic_vector(n-1 downto 0));  
 end nbitserialparalelshiftreg;  
 -- ARCHITECTURE  
 architecture Behavioral of nbitserialparalelshiftreg is  
 -- COMPONENT  
 component nbitregister   
 generic(n:positive:=8);  
   Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       preset : in STD_LOGIC;  
       q : out STD_LOGIC_VECTOR (n-1 downto 0);  
       qnot : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 -- INTERNAL SIGNALS  
 signal sig : std_logic_vector (n downto 0);  
 signal dummy : std_logic_vector (n-1 downto 0);   
 begin  
 sig(0) <= shift_in;  
 -- instantiate an register with generic width 'n' and appropriate connections:  
 reg : nbitregister generic map (n) port map (sig(n-1 downto 0), CLK, reset, preset, sig(n downto 1), dummy);   
 Q_shift <= sig(n downto 1);  
 end Behavioral;  

Test bench:

 LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 ENTITY nbitserialtoparallelshiftregtest IS  
 END nbitserialtoparallelshiftregtest;  
 ARCHITECTURE behavior OF nbitserialtoparallelshiftregtest IS   
   -- Component Declaration for the Unit Under Test (UUT)  
   COMPONENT nbitserialparalelshiftreg  
   PORT(  
      shift_in : IN std_logic;  
      CLK : IN std_logic;  
      reset : IN std_logic;  
      preset : IN std_logic;  
      Q_shift : OUT std_logic_vector(7 downto 0)  
     );  
   END COMPONENT;  
   --Inputs  
   signal shift_in : std_logic := '0';  
   signal CLK : std_logic := '0';  
   signal reset : std_logic := '0';  
   signal preset : std_logic := '0';  
       --Outputs  
   signal Q_shift : std_logic_vector(7 downto 0);  
   -- Clock period definitions  
   constant CLK_period : time := 10 ns;  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
   uut: nbitserialparalelshiftreg PORT MAP (  
      shift_in => shift_in,  
      CLK => CLK,  
      reset => reset,  
      preset => preset,  
      Q_shift => Q_shift  
     );  
 -- SET THE CLOCK PERIOD:  
      clk <= not clk after 50 ns; -- define clock period 100ns  
      tb : PROCESS  
      BEGIN  
           -- Wait 100 ns for global reset to finish  
           wait for 100 ns;  
           -- at this point the contents of the register's flip-flops are undefined  
           -- register contains: UUUUUUUU  
           -- apply asynchronous reset signal:  
           reset <= '1';                       
           -- register now contains: 00000000  
           wait for 50 ns;  
           -- disable reset  
           reset <=     '0';                       
           -- register still contains: 00000000  
           wait for 25 ns;   
           -- after this wait time we have 25 ns left before the first clock that   
           -- the register will shift data on. Now set the shift_in input to '1'  
           shift_in     <= '1';                  
           wait for 800 ns;     -- wait 8 clock periods  
           -- register will shift a '1' in at each clock edge until the shift_in  
           -- value changes:              
           -- clock edge 1: 00000001  
           -- clock edge 2: 00000011  
           -- clock edge 3: 00000111  
           -- clock edge 4: 00001111  
           -- clock edge 5: 00011111  
           -- clock edge 6: 00111111  
           -- clock edge 7: 01111111  
           -- clock edge 8: 11111111  
           shift_in <= '0';                 
           wait for 100 ns; -- wait 1 clock period  
           -- clock edge: 11111110  
           shift_in <= '1';                  
           wait for 300 ns;     -- wait 3 clock periods  
           -- clock edge 1: 11111101  
           -- clock edge 2: 11111011  
           -- clock edge 3: 11110111  
           shift_in <= '0';                 
           wait for 200 ns;   
           -- clock edge 1: 11101110  
           -- clock edge 2: 11011100  
           shift_in <= '1';                      
           wait for 100 ns; -- wait clock period  
           -- clock edge: 10111001  
           wait for 40 ns;  
           -- asynchronous preset  
           preset <= '1';                           
           -- all flipflops are set to 1:  
           -- register now contains: 11111111  
    wait;  
   end process;  
 END;  

Component ( nbit - 4 bit register ) code in the video description

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE