VHDL nbit incrementer structural design code plus test in circuit ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 -----------------------entity inputs and outputs----------------------  
 entity nbitincrementer is  
 generic(n:positive:=4);  
   Port ( ina : in STD_LOGIC_VECTOR (n-1 downto 0);  
       cin : in STD_LOGIC;  
       sum : out STD_LOGIC_VECTOR (n-1 downto 0);  
       cout : out STD_LOGIC);  
 end nbitincrementer;  
 --------------------architecture components and operations----------  
 architecture Behavioral of nbitincrementer is  
 component halfadder   
   Port ( a : in STD_LOGIC;  
       b : in STD_LOGIC;  
       sum : out STD_LOGIC;  
       cout : out STD_LOGIC);  
 end component;  
 signal carryouttob:std_logic_vector(n-2 downto 0);  
 ----------------------port mapping------------------------------  
 begin  
 inst:for i in n-1 downto 0 generate  
 if0:if i=0 generate  
 A: halfadder port map(ina(i),cin,sum(i),carryouttob(i));  
 end generate;  
 if1:if i/=0 and i/=n-1 generate  
 A: halfadder port map(ina(i),carryouttob(i-1),sum(i),carryouttob(i));  
 end generate;  
 if2:if i=n-1 generate  
 A: halfadder port map(ina(i),carryouttob(i-1),sum(i),cout);  
 end generate;  
 end generate;  
 end Behavioral;  

Component ( half adder ) code in the video description

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE