VHDL 3 to 8 decoder code plus test in circuit ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now:

This is another components which will be used to construct the controlled datapath. Refer to the lab sheets:

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 --------------  
 entity three_to_eight_decoder is  
     Port (      OE : in std_logic;  
                      address : in std_logic_vector(2 downto 0);  
       O_outputs : out std_logic_vector(3 downto 0));  
 end three_to_eight_decoder;  
 architecture with_select_arch of three_to_eight_decoder is  
 signal delay : std_logic_vector(3 downto 0) ;  
 signal choice : std_logic_vector (3 downto 0);  
 begin  
 choice(2 downto 0) <= address;  
 choice(3) <= OE;   
 with choice select  
    delay <=  "0001" when "1000",  
          "0010" when "1001",  
          "0100" when "1010",  
          "1000" when "1011",  
          "0000" when others;  
 O_outputs <= delay after 14 ns;  
 end with_select_arch;  

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE