VHDL nbit synchronous counter with enable code plus test in circuit ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 -- ENTITY  
 entity nbit_count_enable is  
       Generic (n : positive := 4);  
   Port ( enable : in std_logic;  
       CLK : in std_logic;  
       reset : in std_logic;  
       Q_outputs : inout std_logic_vector(n-1 downto 0);  
                 ripple_carry_out : out std_logic);  
 end nbit_count_enable;  
 -- ARCHITECTURE  
 architecture Behavioral of nbit_count_enable is  
 -- COMPONENTS  
 component nbitregister is  
      generic(n:positive:=4);  
   Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       preset : in STD_LOGIC;  
       q : out STD_LOGIC_VECTOR (n-1 downto 0);  
       qnot : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 component nbitincrementer  
 generic(n:positive:=4);  
   Port ( ina : in STD_LOGIC_VECTOR (n-1 downto 0);  
       cin : in STD_LOGIC;  
       sum : out STD_LOGIC_VECTOR (n-1 downto 0);  
       cout : out STD_LOGIC);  
 end component;  
 --SIGNALS  
 signal next_state : std_logic_vector (n-1 downto 0);  
 signal dummy : std_logic_vector (n-1 downto 0);  
 signal dummy2: std_logic;  
 begin  
 -- INSTANCES  
 inc : nbitincrementer generic map (n) port map (Q_outputs, enable, next_state, dummy2);  
 reg : nbitregister generic map (n) port map (next_state,clk, reset, '0', Q_outputs, dummy);   
 end Behavioral;  

Component ( nbit register ) code in the video description

Component ( nbit incrementer ) code in the video description

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE