VHDL nbit - 8 bit comparator code plus test in circuit ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 entity bit8Comparator is  
   generic(n:positive:=8);  
       Port ( InA : in STD_LOGIC_VECTOR (n-1 downto 0);  
       InB : in STD_LOGIC_VECTOR (n-1 downto 0);  
       Output : out STD_LOGIC);  
 end bit8Comparator;  
 architecture Behavioral of bit8Comparator is  
 begin  
           process (InA,InB)  
           begin  
           if InA = InB then  
           Output<='1';  
           else  
           Output<='0';  
           end if;  
           end process;  
 end Behavioral;  

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE