electronics blog: VHDL nbit - 6 bit universal shift register structural design code test in circuit ISE Xilinx

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

This is another components used in the structural design. Refer to the lab sheets(lab 3) :

VHDL code:

 library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 entity nbituniversalshiftreg is  
 generic(n:positive:=6);  
   Port ( dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       shiftin : in STD_LOGIC;  
       shiftrotate : in STD_LOGIC;  
       F : in STD_LOGIC_VECTOR (1 downto 0);  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       preset : in STD_LOGIC;  
       qoutputs : out STD_LOGIC_VECTOR (n-1 downto 0)  
                 );  
 end nbituniversalshiftreg;  
 architecture Behavioral of nbituniversalshiftreg is  
 component nBitShiftRotateM   
   generic(n:positive:=6);  
       Port (Data_In1 : in std_logic_vector(n-1 downto 0);  
             Data_In2 : in std_logic_vector(n-1 downto 0);  
             Right_In : in std_logic;  
             Right_Select : in std_logic;  
             Left_In : in std_logic;  
             Left_Select : in std_logic;  
             Control : in std_logic_vector (1 downto 0);  
          Output : o-ut std_logic_vector (n-1 downto 0));  
 end component;  
 component nbitregister   
 generic(n:positive:=6);  
   Port ( Dinputs : in STD_LOGIC_VECTOR (n-1 downto 0);  
       CLK : in STD_LOGIC;  
       reset : in STD_LOGIC;  
       preset : in STD_LOGIC;  
       q : out STD_LOGIC_VECTOR (n-1 downto 0);  
       qnot : out STD_LOGIC_VECTOR (n-1 downto 0));  
 end component;  
 signal toshiftrotate,tonreg,notconnected:std_logic_vector(n-1 downto 0);  
 begin  
 qoutputs<=toshiftrotate;  
 A: nBitShiftRotateM port map(toshiftrotate,dinputs,shiftin,shiftrotate,shiftin,shiftrotate,F,tonreg);  
 B: nbitregister port map(tonreg,CLK,reset,preset,toshiftrotate,qnot=>notconnected);  
 end Behavioral;

Component ( nbit shift rotate ) code in the video description