FPGA VHDL & Verilog 4 bit register file circuit test, testbench and test fixture xilinx spartan 3

VHDL 4 x 4 BIT REGISTER FILE

 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- needed for CONV_INTEGER()
ENTITY register_file IS port(
clk: IN std_logic; --clk
WE: IN std_logic; --write enable
WA: IN std_logic_vector(1 DOWNTO 0); --write address
D: IN std_logic_vector(3 DOWNTO 0); --input
RAE, RBE: IN std_logic; --read enable ports A & B
RAA, RBA: IN std_logic_vector(1 DOWNTO 0); --read address port A & B
PortA, PortB: OUT std_logic_vector(3 DOWNTO 0));--output port A & B
END register_file;
ARCHITECTURE Behavioral OF register_file IS
SUBTYPE reg IS std_logic_vector(3 DOWNTO 0);
TYPE regArray IS array(0 to 3) OF reg;
SIGNAL RF: regArray; --register file contents
BEGIN
WritePort: PROCESS (clk)
BEGIN
IF (clk'EVENT AND clk='1') THEN
IF (WE = '1') THEN
RF(CONV_INTEGER(WA)) <= D; -- fn to convert from vector to integer
END IF;
END IF;
END PROCESS;

ReadPortA: PROCESS (RAA, RAE)
BEGIN
-- Read Port A
IF (RAE = '1') THEN
PortA <= RF(CONV_INTEGER(RAA)); -- fn to convert from vector to integer
ELSE
PortA <= (others => '0');
END IF;
END PROCESS;
ReadPortB: PROCESS (RBE, RBA)
BEGIN
-- Read Port B
IF (RBE = '1') THEN
PortB <= RF(CONV_INTEGER(RBA)); -- fn to convert from vector to integer
ELSE
PortB <= (others => '0');
END IF;
END PROCESS;
END Behavioral;

--One array RF of four elements each element has four bits
--RF(0) => 0000 four bits  
--RF(1) => 0111 four bits
--RF(2) => 0000 four bits
--RF(3) => 0000 four bits

VERILOG 4 x 4 BIT REGISTER FILE

 module register_file_verilog(
input clk,
input WE,//write enable
input [1:0]WA,// --write address
input [3:0]D,// --input
input RAE, RBE,// --read enable ports A & B
input [1:0]RAA, RBA,// --read address port A & B
output reg[3:0]PortA, PortB//--output port A & B
    );

reg [3:0]RF[3:0];
// Write operation
always @(posedge clk)
if (WE==1'b1)
begin 
RF[WA]= D;
end
//read operation port A
always @(posedge clk)
if (RAE==1'b1)
begin 
PortA<=RF[RAA];
end
else
begin
PortA<=0; 
end
//read operation port B
always @(posedge clk)
if (RBE==1'b1)
begin 
PortB<=RF[RBA];
end
else
begin
PortB<=0; 
end

endmodule 

//One array RF of four elements each element has four bits
//RF(0) => 0000 four bits  
//RF(1) => 0000 four bits
//RF(2) => 0011 four bits
//RF(3) => 0000 four bits

VHDL 4 x 4 BIT REGISTER FILE TESTBENCH

 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY registerfileVHDLtest IS
END registerfileVHDLtest;
 
ARCHITECTURE behavior OF registerfileVHDLtest IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT register_file
    PORT(
         clk : IN  std_logic;
         WE : IN  std_logic;
         WA : IN  std_logic_vector(1 downto 0);
         D : IN  std_logic_vector(3 downto 0);
         RAE : IN  std_logic;
         RBE : IN  std_logic;
         RAA : IN  std_logic_vector(1 downto 0);
         RBA : IN  std_logic_vector(1 downto 0);
         PortA : OUT  std_logic_vector(3 downto 0);
         PortB : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal WE : std_logic := '0';
   signal WA : std_logic_vector(1 downto 0) := (others => '0');
   signal D : std_logic_vector(3 downto 0) := (others => '0');
   signal RAE : std_logic := '0';
   signal RBE : std_logic := '0';
   signal RAA : std_logic_vector(1 downto 0) := (others => '0');
   signal RBA : std_logic_vector(1 downto 0) := (others => '0');

 	--Outputs
   signal PortA : std_logic_vector(3 downto 0);
   signal PortB : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk_period : time := 50 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: register_file PORT MAP (
          clk => clk,
          WE => WE,
          WA => WA,
          D => D,
          RAE => RAE,
          RBE => RBE,
          RAA => RAA,
          RBA => RBA,
          PortA => PortA,
          PortB => PortB
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
     RAE<='1';
     RAA<="00";
	  RBE<='1';
     RBA<="00";
	  WAIT FOR 5 ns;
	  RAE<='0';
     RAA<="00";
	  RBE<='0';
     RBA<="00";
	  WAIT FOR 5 ns;
	  WE<='1';
     WA<="00";
	  D<="0001";
	  WAIT FOR 50 ns;
     WE<='1';
     WA<="01";
	  D<="0011";
	  WAIT FOR 50 ns;
     WE<='1';
     WA<="10";
	  D<="0111";
	  WAIT FOR 50 ns;
     WE<='1';
     WA<="11";
	  D<="1111";
	  WAIT FOR 50 ns;
     WE<='0';
     WAIT FOR 50 ns;
     RAE<='1';
     RAA<="00";
	  RBE<='1';
     RBA<="01";
	  WAIT FOR 50 ns;
     RAE<='1';
     RAA<="10";
	  RBE<='1';
     RBA<="11";
	  
	  wait;
   end process;

END;

VERILOG 4 x 4 BIT REGISTER FILE TEST FIXTURE (TESTBENCH)

 
module registerfileVerilogtest;
localparam T=50;
	// Inputs
	reg clk;
	reg WE;
	reg [1:0] WA;
	reg [3:0] D;
	reg RAE;
	reg RBE;
	reg [1:0] RAA;
	reg [1:0] RBA;

	// Outputs
	wire [3:0] PortA;
	wire [3:0] PortB;

	// Instantiate the Unit Under Test (UUT)
	register_file_verilog uut (
		.clk(clk), 
		.WE(WE), 
		.WA(WA), 
		.D(D), 
		.RAE(RAE), 
		.RBE(RBE), 
		.RAA(RAA), 
		.RBA(RBA), 
		.PortA(PortA), 
		.PortB(PortB)
	);
	always
	begin
	clk = 1'b1;
  #(T/2);
  clk = 1'b0;
    #(T/2);
	end

	initial begin
		// Initialize Inputs
	  RAE=1'b1;
     RAA=2'b00;
	  RBE=1'b1;
     RBA=2'b00;
	  #5
	  RAE=1'b0;
     RAA=2'b00;
	  RBE=1'b0;
     RBA=2'b00;
	  #5
	  WE= 1'b1;
     WA= 2'b00;
	  D=4'b0001;
	  #50
     WE= 1'b1;
     WA= 2'b01;
	  D=4'b0011;
	  #50
     WE= 1'b1;
     WA= 2'b10;
	  D=4'b0111;
	  #50
     WE= 1'b1;
     WA= 2'b11;
	  D=4'b1111;
	  #50
     WE= 1'b0;
     #50
     RAE=1'b1;
     RAA=2'b00;
	  RBE=1'b1;
     RBA=2'b01;
	  #50
     RAE=1'b1;
     RAA=2'b10;
	  RBE=1'b1;
     RBA=2'b11;
        
		// Add stimulus here

	end
      
endmodule