FPGA VHDL 4 bit Serial to parallel shift register circuit and test bench comparison Xilinx spartan 3 Waveshare

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FOUR BIT SERIAL TO PARALLEL SHIFT REGISTER

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ShiftReg IS
PORT(Serial_in, Clock, Shift : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 downto 0));
END ShiftReg;
ARCHITECTURE Structural OF ShiftReg IS
SIGNAL N0, N1, N2, N3 : STD_LOGIC;

COMPONENT D_flipflop PORT (D, Clock, E : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END COMPONENT;
BEGIN
U1: D_flipflop PORT MAP (Serial_in, Clock, Shift, N3);
U2: D_flipflop PORT MAP (N3, Clock, Shift, N2);
U3: D_flipflop PORT MAP (N2, Clock, Shift, N1);
U4: D_flipflop PORT MAP (N1, Clock, Shift, N0);
Q(0) <= N3;
Q(1) <= N2;
Q(2) <= N1;
Q(3) <= N0;
END Structural;
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D FLIP FLOP COMPONENT

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY D_flipflop IS
PORT(D, Clock, E : IN STD_LOGIC;
Q : OUT STD_LOGIC);
END D_flipflop;
ARCHITECTURE Behavior OF D_flipflop IS
BEGIN
PROCESS(Clock)
BEGIN
IF (Clock'EVENT AND Clock = '1') THEN
IF (E = '1') THEN
Q <= D;
END IF;
END IF;
END PROCESS;
END Behavior;
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FOUR BIT SERIAL TO PARALLEL SHIFT REGISTER TESTBENCH

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY serialToParallelreg IS
END serialToParallelreg;

ARCHITECTURE behavior OF serialToParallelreg IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT ShiftReg
    PORT(
         Serial_in : IN  std_logic;
         Clock : IN  std_logic;
         Shift : IN  std_logic;
         Q : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
   

   --Inputs
   signal Serial_in : std_logic := '0';
   signal Clock : std_logic := '0';
   signal Shift : std_logic := '0';

  --Outputs
   signal Q : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant Clock_period : time := 100 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: ShiftReg PORT MAP (
          Serial_in => Serial_in,
          Clock => Clock,
          Shift => Shift,
          Q => Q
        );

   -- Clock process definitions
   Clock_process :process
   begin
Clock <= '0';
wait for Clock_period/2;
Clock <= '1';
wait for Clock_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin


Serial_in<='0';
Shift<='0';
wait for 100 ns;
Serial_in<='1';
Shift<='1';
wait for 100 ns;
Serial_in<='0';
Shift<='1';
wait for 100 ns;
Serial_in<='1';
Shift<='1';
wait for 100 ns;
Serial_in<='0';
Shift<='1';


      -- hold reset state for 100 ns.
      wait for 100 ns;

      wait for Clock_period*10;

      -- insert stimulus here

      wait;
   end process;

END;

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CONSTRAINT FILE

NET "Clock"  LOC = "p50"  ; #clock signal coming from the signal generator


#8I/Os_2
NET "Serial_in"  LOC = "p94"  ;
NET "Shift"  LOC = "p93"  ;

#16I/Os_1
NET "Q[3]"  LOC = "p126"  ;
NET "Q[2]"  LOC = "p125"  ;
NET "Q[1]"  LOC = "p124"  ;
NET "Q[0]"  LOC = "p123"  ;

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