FPGA VHDL ALU arithmetic logic unit behavioural and structural approach explanation

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The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:


ALU structural design:

https://www.youtube.com/watch?v=3GOygUhE7KQ&t=25s

The complete vhdl video tutorial structural design at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets(link has ads just wait 5 secs and then skip the ad):

http://viahold.com/y37

Lab guide(link has ads just wait 5 secs and then skip the ad):

http://cogismith.com/1OwP


Files for the ALU structural approach:

http://quitoart.blogspot.co.uk/2017/02/microcontroller-structural-design-vhdl.html

ALU BEHAVIOURAL APPROACH CODE

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LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

-- The following package is needed so that the STD_LOGIC_VECTOR signals

-- A and B can be used in unsigned arithmetic operations.

USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY alu IS PORT (

S: IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- select for operations

A, B: IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- input operands

F: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); -- output

END alu;

ARCHITECTURE Behavior OF alu IS

BEGIN

PROCESS(S, A, B)

BEGIN

CASE S IS

WHEN "000" => -- COMPLEMENT A

F <= (not A);

WHEN "001" => -- AND

F <= A AND B;

WHEN "010" => -- xOR

F <= A XOR B;

WHEN "011" => -- or

F <= A OR B;

WHEN "100" => -- Increment A by 1

F <= A + 1;

WHEN "101" => --  Add: A+B

F <= A + B;

WHEN "110" => -- Decrement A by 1

F <= A - 1;

WHEN OTHERS => -- Subtract: A-B

F <= A - B;

END CASE;

END PROCESS;

END Behavior;

--F2 F1 F0 ALU Operation

--0  0  0  Complement A

--0  0  1     AND

--0  1  0     XOR

--0  1  1     OR

--1  0  0  Increment A by 1

--1  0  1   Add: A+B

--1  1  0  Decrement A by 1

--1  1  1  Subtract: A-B

ALU CONSTRAINT FILE

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NET "S[0]"  LOC = "p51"  ;

NET "S[1]"  LOC = "p43"  ;

NET "S[2]"  LOC = "p44"  ;

#8I/Os_2

NET "A[0]"  LOC = "p94"  ;

NET "A[1]"  LOC = "p93"  ;

NET "A[2]"  LOC = "p92"  ;

NET "A[3]"  LOC = "p91"  ;

NET "B[0]"  LOC = "p88"  ;

NET "B[1]"  LOC = "p87"  ;

NET "B[2]"  LOC = "p86"  ;

NET "B[3]"  LOC = "p85"  ;

#16I/Os_1

NET "F[0]"  LOC = "p126"  ;

NET "F[1]"  LOC = "p125"  ;

NET "F[2]"  LOC = "p124"  ;

NET "F[3]"  LOC = "p123"  ;

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TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE