FPGA Verilog D flip flop with asynchronous reset and preset xilinx spartan 3

This video is part of a series to design a Controlled Datapath using a structural approach in Verilog. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete vhdl video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

D flip flop

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module d_ff_reset

   (

    input wire clk, reset,preset,

    input wire d,

    output reg q,qnot

   );

   // body

   always @(posedge clk, posedge reset,posedge preset)

      

if (reset)begin

         q <= 1'b0;

qnot <= 1'b1;

      end

else if (preset)begin

         q <= 1'b1;

qnot <= 1'b0;

      end

else 

begin

         q <= d;

qnot <= ~d;

end

endmodule

// clk       D    Preset Reset   Q        Qnot

// rising    0       0     0     0         1

// rising    1       0     0     1         0

//    0      -       0     0    last Q    last Qnot

//    1      -       0     0    last Q    last Qnot

//    -      -       1     0     1         0

//    -      -       -     1     0         1

CONSTRAINTS
-----------------------------------------------------------------------------------------------------------------


#8I/Os_2
NET "d"  LOC = "p94"  ;
NET "reset"  LOC = "p93"  ;
NET "preset"  LOC = "p92"  ;
NET "clk"  LOC = "p50"  ;

#16I/Os_1
NET "q"  LOC = "p126"  ;
NET "qnot"  LOC = "p125"  ;

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TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE