electronics blog: FPGA Verilog Data Path structural design simulation test fixture testbench with clock signal generated

This video is part of a series which final design is a Controlled Datapath using a structural approach. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units,etc.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as intructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide, Data path and control words, Controller and next state logic to manipulate the datapath:

https://yadi.sk/d/Xe62M3Ds3MoVMD

Final design files download:

http://quitoart.blogspot.co.uk/2017/02/microcontroller-structural-design-vhdl.html

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Final Controlled datapath VHDL design video:

Datapath and controller internals:

Parts working on now (the datapath):

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CONTROL WORDS USED IN THE DATAPATH (ONES COUNTER) refer to the learning material

Lab guide, Data path and control words, Controller and next state logic to manipulate the datapath:

https://yadi.sk/d/Xe62M3Ds3MoVMD

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DATAPATH MODULE

module Data_path(

input [3:0]Input,
input S,
input [2:0]Write_address,
input Write_enable,
input [2:0]Read_address_A,
input Read_Enable_A,
input [2:0]Read_address_B,
input Read_Enable_B,
input [2:0]Function_arith_or_logic,
input [2:0]G,
output [3:0]Status,
input en,
input clk,
output [3:0]Output
);

wire [3:0]status,toRCF,BusA,BusB,ALU_toshifter,shifter_to_output_reg;
nbit_two_input_multiplexer mux_component(status,Input,S,toRCF);
RCF_eight_x_n RCF_component(toRCF,Read_address_A,Read_address_B,Write_address,Read_Enable_A,Read_Enable_B,Write_enable,clk,BusA,BusB);
ALU alu_component(BusA,BusB,Function_arith_or_logic,ALU_toshifter);
four_input_or_gate status_component(ALU_toshifter,Status);
shifter_rotator shifter_component(ALU_toshifter,G,shifter_to_output_reg);
nbitregister_loadhold output_reg(shifter_to_output_reg,en,clk,1'b0,1'b0,Output);

endmodule

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DATAPATH TEST FIXTURE

`timescale 1ns / 1ps

module DP_test;
localparam T=20;
// Inputs
reg [3:0] Input;
reg S;
reg [2:0] Write_address;
reg Write_enable;
reg [2:0] Read_address_A;
reg Read_Enable_A;
reg [2:0] Read_address_B;
reg Read_Enable_B;
reg [2:0] Function_arith_or_logic;
reg [2:0] G;
reg en;
reg clk;

// Outputs
wire [3:0] Status;
wire [3:0] Output;

// Instantiate the Unit Under Test (UUT)
Data_path uut (
.Input(Input),
.S(S),
.Write_address(Write_address),
.Write_enable(Write_enable),
.Read_address_A(Read_address_A),
.Read_Enable_A(Read_Enable_A),
.Read_address_B(Read_address_B),
.Read_Enable_B(Read_Enable_B),
.Function_arith_or_logic(Function_arith_or_logic),
.G(G),
.Status(Status),
.en(en),
.clk(clk),
.Output(Output)
);

always begin
clk = 1'b1;
#(T/2);
clk = 1'b0;
#(T/2);
end

initial begin
// Initialize Inputs
#50
Input = 0;
S = 0;
Write_address = 0;
Write_enable = 0;
Read_address_A = 0;
Read_Enable_A = 0;
Read_address_B = 0;
Read_Enable_B = 0;
Function_arith_or_logic = 0;
G = 0;
en = 0;

////////////////////////////////////////////////

#50
Input = 4'b0100;// input binary 4
S = 1'b1; //input enabled
Write_address = 3'b000; // input stored in address binary 0
Write_enable = 1'b1;//write enabled
Read_address_A = 3'b000;
Read_Enable_A = 1'b0;
Read_address_B = 3'b000;
Read_Enable_B = 1'b0;
Function_arith_or_logic = 3'b000;
G = 3'b000;
en = 1'b0;

#50
Input = 4'b0000;
S = 1'b0;
Write_address = 3'b001;//store result of the operation done in the ALU in address binary 1 the result is 1000
Write_enable = 1'b1;//write in address enabled
Read_address_A = 3'B000;//read address 0 in A
Read_Enable_A = 1'b1;//read enabled
Read_address_B = 3'b000;//read address 0 in B
Read_Enable_B = 1'b1;//read enabled
Function_arith_or_logic = 3'b101;//add A + B = 100+100=1000
G = 3'b000;
en = 1'b1;

///////////////////////////////////////////////

// Wait 100 ns for global reset to finish
#100;

// Add stimulus here

end

endmodule

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4 BIT TWO INPUT MULTIPLEXER COMPONENT