FPGA VHDL & Verilog binary UP and DOWN behavioural counter circuit test, testbench and test fixture

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VHDL UP DOWN COUNTER

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY UpDownCounter IS PORT (

clk: IN STD_LOGIC;

Clear: IN STD_LOGIC;

Count: IN STD_LOGIC;

Down: IN STD_LOGIC;

Q: OUT INTEGER RANGE 0 TO 15);

END UpDownCounter;

ARCHITECTURE Behavioral OF UpDownCounter IS

BEGIN

PROCESS (clk, Clear)

VARIABLE value: INTEGER RANGE 0 TO 15;

BEGIN

IF (Clear = '1') THEN

value := 0;

ELSIF (clk'EVENT AND clk='1') THEN

IF (Count = '1') THEN

IF (Down = '0') THEN

value := value + 1;

ELSE

value := value - 1;

END IF;

END IF;

END IF;

Q <= value;

END PROCESS;

END Behavioral;

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VHDL UP DOWN COUNTER TEST BENCH

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

 

ENTITY updowncounterVHDLtest IS

END updowncounterVHDLtest;

 

ARCHITECTURE behavior OF updowncounterVHDLtest IS 

 

    -- Component Declaration for the Unit Under Test (UUT)

 

    COMPONENT UpDownCounter

    PORT(

         clk : IN  std_logic;

         Clear : IN  std_logic;

         Count : IN  std_logic;

         Down : IN  std_logic;

         Q : OUT  INTEGER RANGE 0 TO 15

        );

    END COMPONENT;

    

   --Inputs

   signal clk : std_logic := '0';

   signal Clear : std_logic := '0';

   signal Count : std_logic := '0';

   signal Down : std_logic := '0';

  --Outputs

   signal Q : INTEGER RANGE 0 TO 15;

   -- Clock period definitions

   constant clk_period : time := 50 ns;

 

BEGIN

 

-- Instantiate the Unit Under Test (UUT)

   uut: UpDownCounter PORT MAP (

          clk => clk,

          Clear => Clear,

          Count => Count,

          Down => Down,

          Q => Q

        );

   -- Clock process definitions

   clk_process :process

   begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;

   end process;

 

   -- Stimulus process

   stim_proc: process

   begin

      -- hold reset state for 100 ns.

      

Clear <= '1';

Count <= '0';

Down <= '0';

wait for 20 ns;

Clear <= '0';

Count <= '1';

Down <= '0';

      wait for 300 ns; 

Clear <= '0';

Count <= '1';

Down <= '1';

      wait for 100 ns;

Clear <= '1';

Count <= '1';

Down <= '1';

      wait for 20 ns;

Clear <= '0';

Count <= '1';

Down <= '0';

   

      -- insert stimulus here 

      wait;

   end process;

END;

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VERILOG UP DOWN COUNTER

module BinaryUpCounterVerilog(

input clk,

input Clear,

input Count,

input Down,

output wire[3:0]Q

 );

reg [3:0]value;

always @(posedge clk,posedge Clear)

if (Clear)

value <= 0;

else if (Count==1'b1) 

begin

if (Down==1'b0)

begin

value <= value + 1 ;

assign Q = value;

end

else if (Down==1'b1)

begin

value <= value - 1 ;

assign Q = value;

end

end

endmodule

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VERILOG UP DOWN COUNTER TEST FIXTURE

module binaryupcounttestbench;

localparam T=50;

// Inputs

reg clk;

reg clear;

reg count;

// Outputs

wire [3:0] Q;

// Instantiate the Unit Under Test (UUT)

BinaryUpCounterVerilog uut (

.clk(clk), 

.clear(clear), 

.count(count), 

.Q(Q)

);

always begin

    clk = 1'b1;

  #(T/2);

  clk = 1'b0;

    #(T/2);

  end

initial begin

      clear=1'b0;

      count=1'b1;

      # 20 

clear=1'b1;

      count=1'b1;

      #20

clear=1'b0;

      count=1'b1;

      #500

clear=1'b1;

      count=1'b1;

      #20

clear=1'b0;

      count=1'b1;

end

      

endmodule

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CONSTRAINTS

NET "clk" LOC = "P58";

#8I/Os_2

NET "count"  LOC = "p94"  ;

NET "clear"  LOC = "p93"  ;

#16I/Os_1

NET "Q[0]"  LOC = "p126"  ;

NET "Q[1]"  LOC = "p125"  ;

NET "Q[2]"  LOC = "p124"  ;

NET "Q[3]"  LOC = "p123"  ;