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4 BIT SERIAL TO PARALLEL AND PARALLEL TO SERIAL SHIFT REGISTER
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY shiftreg IS PORT (
Clock: IN STD_LOGIC;
SHSel: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Serial_in: IN STD_LOGIC;
D: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Serial_out: OUT STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END shiftreg;
ARCHITECTURE Behavioral OF shiftreg IS
SIGNAL content: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(Clock)
BEGIN
IF (Clock'EVENT AND Clock='1') THEN
CASE SHSel IS
WHEN "01" => -- load
content <= D;
WHEN "10" => -- shift right, pad with bit from Serial_in
content <= Serial_in & content(3 DOWNTO 1);
WHEN OTHERS =>
NULL;
END CASE;
END IF;
END PROCESS;
Q <= content;
Serial_out <= content(0);
END Behavioral;
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TESTBENCH
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY serial2paralleltest IS
END serial2paralleltest;
ARCHITECTURE behavior OF serial2paralleltest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT shiftreg
PORT(
Clock : IN std_logic;
SHSel : IN std_logic_vector(1 downto 0);
Serial_in : IN std_logic;
D : IN std_logic_vector(3 downto 0);
Serial_out : OUT std_logic;
Q : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal Clock : std_logic := '0';
signal SHSel : std_logic_vector(1 downto 0) := (others => '0');
signal Serial_in : std_logic := '0';
signal D : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal Serial_out : std_logic;
signal Q : std_logic_vector(3 downto 0);
-- Clock period definitions
constant Clock_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: shiftreg PORT MAP (
Clock => Clock,
SHSel => SHSel,
Serial_in => Serial_in,
D => D,
Serial_out => Serial_out,
Q => Q
);
-- Clock process definitions
Clock_process :process
begin
Clock <= '0';
wait for Clock_period/2;
Clock <= '1';
wait for Clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
D<= "0101";
SHSel <= "01";
wait for 100 ns;
SHSel <= "10";
wait for 300 ns;
SHSel <= "10";
Serial_in<= '1';
wait for 100 ns;
SHSel <= "10";
Serial_in<= '0';
wait for 100 ns;
SHSel <= "10";
Serial_in<= '1';
wait for 100 ns;
SHSel <= "10";
Serial_in<= '0';
-- hold reset state for 100 ns.
wait for 100 ns;
--wait for Clock_period*10;
-- insert stimulus here
wait;
end process;
END;
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CONSTRAINTS
NET "Clock" LOC = "p58" ;
#8I/Os_2
NET "Serial_in" LOC = "p85" ;
#8I/Os_2
NET "D[3]" LOC = "p94" ;
NET "D[2]" LOC = "p93" ;
NET "D[1]" LOC = "p92" ;
NET "D[0]" LOC = "p91" ;
NET "SHSel[0]" LOC = "p43" ;
NET "SHSel[1]" LOC = "p44" ;
#16I/Os_1
NET "Q[3]" LOC = "p126" ;
NET "Q[2]" LOC = "p125" ;
NET "Q[1]" LOC = "p124" ;
NET "Q[0]" LOC = "p123" ;
NET "Serial_out" LOC = "p113" ;
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