electronics blog: FPGA Verilog 4 bit register file cell RFC structural design xilinx spartan 3

This video is part of a series to design a Controlled Datapath using a structural approach in Verilog. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete vhdl video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now:

Refer to the lab sheets lab 5 for the register file cell internals

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4 BIT RFC REGISTER FILE CELL TOP MODULE STRUCTURAL DESIGN

(the video is from the VHDL version but demonstrates what the circuit should do)

module RCF_register_4bit
#(parameter N=4)
(
input [N-1:0]DIN,
input REA,
input REB,
input WE,
input clk,
output [N-1:0]OA,
output [N-1:0]OB
);

genvar i;

generate
for(i=0;i begin: instantiating_RFC

RCF_register_1bit multiple_instance(DIN[i],REA,REB,WE,clk,OA[i],OB[i]);

end
endgenerate

endmodule

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-----------------------------------------------------------------
1 BIT RFC COMPONENT

CODE:
http://quitoart.blogspot.co.uk/2017/09/fpga-verilog-1-bit-register-file-cell.html
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1 BIT TWO INPUT MULTIPLEXER MODULE