electronics blog: FPGA Verilog 8 x nbit bit register file cell register RFC xilinx spartan 3 waveshare development board

This video is part of a series to design a Controlled Datapath using a structural approach in Verilog. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete vhdl video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

Parts working on now:

Refer to the lab sheets lab 5 for the register file cell internals

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(the video is from the VHDL version but demonstrates what the circuit should do)

8 X 4 BIT RFC REGISTER FILE CELL TOP MODULE STRUCTURAL DESIGN

module RCF_eight_x_n(

input [3:0]Data_in,
input [2:0]Read_address_A,
input [2:0]Read_address_B,
input [2:0]write_address,
input REA,
input REB,
input WE,
input clk,
output [3:0]outA,
output [3:0]outB

);
wire [3:0]REA_signal;
wire [3:0]REB_signal;
wire [3:0]WE_signal;
three_to_four_decoder REA_instance(REA,Read_address_A,REA_signal);
three_to_four_decoder REB_instance(REB,Read_address_B,REB_signal);
three_to_four_decoder WE_instance(WE,write_address,WE_signal);

genvar i;

generate
for(i=0;i<4 i="i+1)</p"> begin: instantiating_RFCs

RCF_register_4bit instances(Data_in,REA_signal[i],REB_signal[i],WE_signal[i],clk,outA,outB);
end
endgenerate

endmodule

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4 BIT RFC REGISTER FILE CELL STRUCTURAL DESIGN

(the video is from the VHDL version but demonstrates what the circuit should do)

CODE:

http://quitoart.blogspot.co.uk/2017/09/fpga-verilog-4-bit-register-file-cell.html
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3 TO 8 DECODER(THE CODE for this design was MODIFIED FOR FOUR BITS THE VIDEO SHOWS THE ORIGINAL 3 TO 8 DECODER), so the module in this design is a 3 to 4 decoder

(3 TO FOUR DECODER USED IN THIS DESIGN)
module three_to_four_decoder
(
input OE,
input [2:0]address,
output reg [3:0]O_outputs);

wire [3:0]choice;
assign choice = {OE,address};
always @*
case (choice)
4'b1000 : O_outputs <= 4'b0001;
4'b1001 : O_outputs <= 4'b0010;
4'b1010 : O_outputs <= 4'b0100;
4'b1011 : O_outputs <= 4'b1000;
default : O_outputs <= 4'b0000;
endcase

endmodule

CODE:(Original 3 to 8 decoder)
http://quitoart.blogspot.co.uk/2017/09/fpga-verilog-3-to-8-decoder-xilinx.html
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1 BIT RFC COMPONENT

CODE:
http://quitoart.blogspot.co.uk/2017/09/fpga-verilog-1-bit-register-file-cell.html
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1 BIT TWO INPUT MULTIPLEXER MODULE