FPGA Verilog 1 bit register file cell RFC structural design xilinx spartan 3

This video is part of a series to design a Controlled Datapath using a structural approach in Verilog. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete vhdl video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

The design in this lab covers the basics of microcontrolller structural design

Intended Controlled datapath design design:

Datapath and controller internals:

     

Parts working on now:

Refer to the lab sheets lab 5 for the register file cell internals

TOP 1 BIT REGISTER FILE CELL MODULE(the video is from the VHDL version but demostrates what the circuit should do)
----------------------------------------------------------
module RCF_register_1bit(
input DIN,
input REA,
input REB,
input WE,
input clk,
output OA,
output OB
    );

wire dff_out_to_mux,muxto_dff,q_not;
d_ff_reset dff_instance(.d(muxto_dff),.reset(1'b0),.preset(1'b0),.clk(clk),.q(dff_out_to_mux),.qnot(q_not));
two_input_multiplexer mux_instance(.bin0(dff_out_to_mux),.bin1(DIN),.sel(WE),.mux_out(muxto_dff));
tri_state_buffer buffer_componentA(dff_out_to_mux,REA,OA);
tri_state_buffer buffer_componentB(dff_out_to_mux,REB,OB);
endmodule

----------------------------------------------------------

1 BIT TWO INPUT MULTIPLEXER MODULE

Code:

http://quitoart.blogspot.co.uk/2017/08/fpga-verilog-1-bit-two-input.html

----------------------------------------------------------

D FLIP FLOP WITH ASYNCHRONOUS RESET PRESET MODULE

Code:

http://quitoart.blogspot.co.uk/2017/09/fpga-verilog-d-flip-flop-with.html

----------------------------------------------------------
TRI STATE BUFFER COMPONENT

CODE:

http://quitoart.blogspot.co.uk/2017/09/fpga-verilog-tristate-buffer-xilinx.html

----------------------------------------------------------

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE

TUTORIAL TO CREATE A SQUARE WAVE GENERATOR TO CLOCK THE CIRCUIT
This is an alternative to clock the circuits another method is shown in the tutorial above