FPGA Verilog four bit register using a d flip flop for loop instantiation

This video is part of a series to design a Controlled Datapath using a structural approach in Verilog. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete vhdl video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

FOUR BIT REGISTER
--------------------------------------------------------------------------------------------
module nbitregister
#(parameter N=4)
(
input clk,
input [N-1:0]D_input,
input reset,
input preset,
output [N-1:0]Q_output,
output [N-1:0]Q_bar_output
    );

genvar i;
generate
for(i=0;i begin: dff_instantiation
d_ff_reset dff_instance(.clk(clk),.reset(reset),.preset(preset),.d(D_input[i]),.q(Q_output[i]),.qnot(Q_bar_output[i]));
end
endgenerate
endmodule

D FLIP FLOP COMPONENT

--------------------------------------------------------------------------------------------


// Listing 4.2
module d_ff_reset
   (
    input wire clk, reset,preset,
    input wire d,
    output reg q,qnot
   );

   // body
   always @(posedge clk, posedge reset,posedge preset)
      if (reset)begin
         q <= 1'b0;
qnot <= 1'b1;
      end
else if (preset)begin
         q <= 1'b1;
qnot <= 1'b0;
      end
else
begin
         q <= d;
qnot <= ~d;
end
endmodule


// clk       D    Preset Reset   Q        Qnot
// rising    0       0     0     0         1
// rising    1       0     0     1         0
//    0      -          0     0    last Q    last Qnot
//    1      -          0     0    last Q    last Qnot
//    -      -          1     0     1         0
//    -      -           -     1     0         1

FOUR BIT REGISTER CONSTRAINT
--------------------------------------------------------------------------------------------

NET "clk" LOC = "P50" ;

#8I/Os_2
NET "D_input[0]"  LOC = "p94"  ;
NET "D_input[1]"  LOC = "p93"  ;
NET "D_input[2]"  LOC = "p92"  ;
NET "D_input[3]"  LOC = "p91"  ;

NET "reset"  LOC = "p51"  ;
NET "preset"  LOC = "p43"  ;


#16I/Os_1
NET "Q_output[0]"  LOC = "p126"  ;
NET "Q_output[1]"  LOC = "p125"  ;
NET "Q_output[2]"  LOC = "p124"  ;
NET "Q_output[3]"  LOC = "p123"  ;
NET "Q_bar_output[0]"  LOC = "p122"  ;
NET "Q_bar_output[1]"  LOC = "p117"  ;
NET "Q_bar_output[2]"  LOC = "p116"  ;
NET "Q_bar_output[3]"  LOC = "p113"  ;

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE

TUTORIAL TO CREATE A SQUARE WAVE GENERATOR TO CLOCK THE CIRCUIT
This is an alternative to clock the circuits another method is shown in the tutorial above