FPGA VHDL & Verilog binary up counter circuit test, testbench and test fixture

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VHDL BINARY UP COUNTER

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; -- need this to add STD_LOGIC_VECTORs
ENTITY BinaryUpCounter IS PORT (
clk: IN STD_LOGIC;
Clear: IN STD_LOGIC;
Count: IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END BinaryUpCounter;
ARCHITECTURE Behavioral OF BinaryUpCounter IS
SIGNAL value: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS (clk, Clear)
BEGIN
IF Clear = '1' THEN
value <= (OTHERS => '0'); -- 4-bit vector of 0, same as "0000"
ELSIF (clk'EVENT AND clk='1') THEN
IF Count = '1' THEN
value <= value + 1;
END IF;
END IF;
END PROCESS;
Q <= value;
END Behavioral;

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VHDL TEST BENCH

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY binaryupcounttestvhd IS
END binaryupcounttestvhd;

ARCHITECTURE behavior OF binaryupcounttestvhd IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT counter
    PORT(
         clk : IN  std_logic;
         Clear : IN  std_logic;
         Count : IN  std_logic;
         Q : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
   

   --Inputs
   signal clk : std_logic := '0';
   signal Clear : std_logic := '0';
   signal Count : std_logic := '0';

  --Outputs
   signal Q : std_logic_vector(3 downto 0);

   -- Clock period definitions
   constant clk_period : time := 50 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
   uut: counter PORT MAP (
          clk => clk,
          Clear => Clear,
          Count => Count,
          Q => Q
        );

   -- Clock process definitions
   clk_process :process
   begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
   end process;


   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 100 ns.
      clear<='0';
      count<='1';
      wait for 20 ns;
clear<='1';
      count<='1';
      wait for 20 ns;
clear<='0';
      count<='1';
      wait for 500 ns;
clear<='1';
      count<='1';
      wait for 20 ns;
clear<='0';
      count<='1';
     
      -- insert stimulus here

      wait;
   end process;

END;

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VERILOG BINARY UP COUNTER

module BinaryUpCounterVerilog(

input clk,

input clear,

input count,

output wire[3:0]Q

 );

reg [3:0]value;

always @(posedge clk,posedge clear)

if (clear)

value <= 0;

else if (count==1'b1) 

begin

value <= value + 1 ;

end

assign Q = value;

endmodule

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VERILOG TEST BENCH (TEST FIXTURE)

module binaryupcounttestbench;

localparam T=50;

// Inputs

reg clk;

reg clear;

reg count;

// Outputs

wire [3:0] Q;

// Instantiate the Unit Under Test (UUT)

BinaryUpCounterVerilog uut (

.clk(clk), 

.clear(clear), 

.count(count), 

.Q(Q)

);

always begin

    clk = 1'b1;

  #(T/2);

  clk = 1'b0;

    #(T/2);

  end

initial begin

      clear=1'b0;

      count=1'b1;

      # 20 

clear=1'b1;

      count=1'b1;

      #20

clear=1'b0;

      count=1'b1;

      #500

clear=1'b1;

      count=1'b1;

      #20

clear=1'b0;

      count=1'b1;

end

      

endmodule

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CONSTRAINTS

NET "clk" LOC = "P58";

#8I/Os_2

NET "count"  LOC = "p94"  ;

NET "clear"  LOC = "p93"  ;

#16I/Os_1

NET "Q[0]"  LOC = "p126"  ;

NET "Q[1]"  LOC = "p125"  ;

NET "Q[2]"  LOC = "p124"  ;

NET "Q[3]"  LOC = "p123"  ;