This video is part of a series to design a Controlled Datapath using a structural approach in Verilog. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units.
The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:
The complete vhdl video tutorial at:
https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4
Lab Sheets:
http://viahold.com/y37
Lab guide
http://cogismith.com/1OwP
Intended design:
Datapath and controller internals:
Parts working on now:
Shifter components
Files download
SHIFTER ROTATOR TOP MODULE (module being tested in the above video)
----------------------------------------------------------------------------------------------------------------
module shifter_rotator(
input [3:0]Data_In,
input [2:0]G,
output [3:0]Output
);
wire [1:0]to_shift_rotator;
shift_control_logic shift_logic_component(G,to_shift_rotator);
four_bit_shifter_rotator_unit shifter_component(Data_In,4'b0000,G[0],G[1],G[0],G[1],to_shift_rotator,Output);
endmodule
// G2 G1 G0 shifter operation
// 000 PASS
// 001 rotate lef
// 010 shift left input a 0
// 011 shift left input a 1
// 100 PASS
// 101 rotate right
// 110 shift right input a 0
// 111 shift right input a 1
----------------------------------------------------------------------------------------------------------------
SHIFT CONTROL LOGIC
----------------------------------------------------------------------------------------------------------------
module shift_control_logic(
input [2:0]In,
output [1:0]Output
);
assign Output[0] = ~In[2] & (In[1] | In[0]);
assign Output[1] = In[2] & (In[1] | In[0]);
endmodule
----------------------------------------------------------------------------------------------------------------
1 BIT FOUR TO ONE MULTIPLEXER
----------------------------------------------------------------------------------------------------------------
module four_input_multiplexer(
input a,
input b,
input c,
input d,
input [1:0] Control,
output reg Output
);
always @(Control,a,b,c,d)
begin
case (Control)
2'b00:Output = a;
2'b01:Output = b;
2'b10:Output = c;
2'b11:Output = d;
endcase
end
endmodule
On the right are the internal components of the shifter rotator the code for all components are on this page just scroll down.
FOUR BIT SHIFTER ROTATOR UNIT COMPONENT
#(parameter N=4)
(
input [N-1:0]Data_In1,
input [N-1:0]Data_In2,
input Right_In,
input Right_Select,
input Left_In,
input Left_Select,
input [1:0]Control,
output [N-1:0] Output
);
wire left_multiplexer,right_multiplexer;
two_input_multiplexer right_mux(Data_In1[N-1],Right_In,Right_Select,right_multiplexer);
two_input_multiplexer left_mux(Data_In1[0],Left_In,Left_Select,left_multiplexer);
genvar i;
generate
for(i=0;i begin: cheking_instances
if(i==N-1)
begin
four_input_multiplexer last_instance(Data_In1[i],Data_In1[i-1],left_multiplexer,Data_In2[i],Control,Output[i]);
end
else if((i0))
begin
four_input_multiplexer other_instances(Data_In1[i],Data_In1[i-1],Data_In1[i+1],Data_In2[i],Control,Output[i]);
end
else if(i==0)
begin
four_input_multiplexer first_instance(Data_In1[i],right_multiplexer,Data_In1[i+1],Data_In2[i],Control,Output[i]);
end
end
endgenerate
endmodule
DOWNLOAD FILES<=
4 BIT ALU ARITHMETIC LOGIC UNIT
input [3:0]InA,
input [3:0]InB,
input [2:0]F,
output [3:0]Output,
output C_out );
wire [3:0]logic_unit_to_mux;
wire [3:0]arithmetic_unit_to_mux;
four_bit_arithmetic_unit arithmetic_unit_component(InA,InB,F[1:0],arithmetic_unit_to_mux,C_out);
four_bit_logic_unit logic_component(InA,InB,F[1:0],logic_unit_to_mux);
nbit_two_input_multiplexer mux_component(logic_unit_to_mux,arithmetic_unit_to_mux,F[2],Output);
endmodule
//F2 F1 F0 ALU operation
// 000 Complement A
// 001 and
// 010 xor
// 011 or
// 100 A+1
// 101 A+B
// 110 A-1
// 111 A-B
4 BIT LOGIC UNIT COMPONENT
----------------------------------------------------------------------------------------------------------------
1 BIT LOGIC UNIT COMPONENT
module one_bit_logic_function(
input a,
input b,
input [1:0] Control,
output reg Output
);
always @*
begin
case (Control)
2'b00: Output = ~a;
2'b01: Output = a & b;
2'b10: Output = a ^ b;
2'b11: Output = a | b;
endcase
end
endmodule
DOWNLOAD FILES <=
FOUR BIT ARITHMETIC UNIT STRUCTURAL DESIGN
----------------------------------------------------------------------------------------------------------------
module four_bit_arithmetic_unit
#(parameter N=4)
(
input [N-1:0]InA,
input [N-1:0]InB,
input [1:0]Control,
output [N-1:0]Sum,
output C_out
);
//assign InA =assig_to_A;
wire [N-1:0]mux_to_addersub;
nbit_two_input_multiplexer mux_component(4'b0001,InB,Control[0],mux_to_addersub);
nbit_adder_subtractor add_subtractor_component(InA,mux_to_addersub,Control[1],Sum,C_out);
endmodule
//Control arithmetic function
// 00 A+1
// 01 A+B
// 10 A-1
// 11 A-B
----------------------------------------------------------------------------------------------------------------
FOUR BIT TWO INPUT MULTIPLEXER STRUCTURAL DESIGN
----------------------------------------------------------------------------------------------------------------
module nbit_two_input_multiplexer
#(parameter N=4)
(input [N-1:0]bin0,
input [N-1:0]bin1,
input sel,
output [N-1:0]mux_out);
genvar i;
generate
for (i=0;i begin: generate_mux
two_input_multiplexer mux(.bin0(bin0[i]),.bin1(bin1[i]),.sel(sel),.mux_out(mux_out[i]));
end
endgenerate
endmodule
----------------------------------------------------------------------------------------------------------------
1 BIT TWO INPUT MULTIPLEXER
----------------------------------------------------------------------------------------------------------------
module two_input_multiplexer(
input wire bin0,
input wire bin1,
input wire sel,
output mux_out
);
//if select is 0 chose bin0 otherwise bin1
assign mux_out = sel ? bin1 : bin0 ;
endmodule
----------------------------------------------------------------------------------------------------------------
ADDER SUBTRACTOR TOP MODULE
----------------------------------------------------------------------------------------------------------------
module nbit_adder_substractor
#(parameter N=4)
( input [N-1:0]InA,
input [N-1:0]InB,
input Control,
output [N-1:0]Sum,
output C_out
);
wire [N-1:0]xor_to_adder;
four_bit_LAC_adder adder_component(InA,xor_to_adder,Control,Sum,C_out);
nbit_xor_gate_control xor_componet(InB,Control,xor_to_adder);
endmodule
The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:
The complete vhdl video tutorial at:
https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4
Lab Sheets:
http://viahold.com/y37
Lab guide
http://cogismith.com/1OwP
Intended design:
Datapath and controller internals:
Parts working on now:
SHIFTER ROTATOR TOP MODULE (module being tested in the above video)
----------------------------------------------------------------------------------------------------------------
input [3:0]Data_In,
input [2:0]G,
output [3:0]Output
);
wire [1:0]to_shift_rotator;
shift_control_logic shift_logic_component(G,to_shift_rotator);
four_bit_shifter_rotator_unit shifter_component(Data_In,4'b0000,G[0],G[1],G[0],G[1],to_shift_rotator,Output);
endmodule
// G2 G1 G0 shifter operation
// 000 PASS
// 001 rotate lef
// 010 shift left input a 0
// 011 shift left input a 1
// 100 PASS
// 101 rotate right
// 110 shift right input a 0
// 111 shift right input a 1
----------------------------------------------------------------------------------------------------------------
SHIFT CONTROL LOGIC
----------------------------------------------------------------------------------------------------------------
module shift_control_logic(
input [2:0]In,
output [1:0]Output
);
assign Output[0] = ~In[2] & (In[1] | In[0]);
assign Output[1] = In[2] & (In[1] | In[0]);
endmodule
1 BIT FOUR TO ONE MULTIPLEXER
----------------------------------------------------------------------------------------------------------------
module four_input_multiplexer(
input a,
input b,
input c,
input d,
input [1:0] Control,
output reg Output
);
always @(Control,a,b,c,d)
begin
case (Control)
2'b00:Output = a;
2'b01:Output = b;
2'b10:Output = c;
2'b11:Output = d;
endcase
end
endmodule
----------------------------------------------------------------------------------------------------------------
On the right are the internal components of the shifter rotator the code for all components are on this page just scroll down.
FOUR BIT SHIFTER ROTATOR UNIT COMPONENT
----------------------------------------------------------------------------------------------------------------
module four_bit_shifter_rotator_unit#(parameter N=4)
(
input [N-1:0]Data_In1,
input [N-1:0]Data_In2,
input Right_In,
input Right_Select,
input Left_In,
input Left_Select,
input [1:0]Control,
output [N-1:0] Output
);
wire left_multiplexer,right_multiplexer;
two_input_multiplexer right_mux(Data_In1[N-1],Right_In,Right_Select,right_multiplexer);
two_input_multiplexer left_mux(Data_In1[0],Left_In,Left_Select,left_multiplexer);
genvar i;
generate
for(i=0;i
if(i==N-1)
begin
four_input_multiplexer last_instance(Data_In1[i],Data_In1[i-1],left_multiplexer,Data_In2[i],Control,Output[i]);
end
else if((i
begin
four_input_multiplexer other_instances(Data_In1[i],Data_In1[i-1],Data_In1[i+1],Data_In2[i],Control,Output[i]);
end
else if(i==0)
begin
four_input_multiplexer first_instance(Data_In1[i],right_multiplexer,Data_In1[i+1],Data_In2[i],Control,Output[i]);
end
end
endgenerate
endmodule
----------------------------------------------------------------------------------------------------------------
DOWNLOAD FILES<=
4 BIT ALU ARITHMETIC LOGIC UNIT
----------------------------------------------------------------------------------------------------------------
module ALU(input [3:0]InA,
input [3:0]InB,
input [2:0]F,
output [3:0]Output,
output C_out );
wire [3:0]logic_unit_to_mux;
wire [3:0]arithmetic_unit_to_mux;
four_bit_arithmetic_unit arithmetic_unit_component(InA,InB,F[1:0],arithmetic_unit_to_mux,C_out);
four_bit_logic_unit logic_component(InA,InB,F[1:0],logic_unit_to_mux);
nbit_two_input_multiplexer mux_component(logic_unit_to_mux,arithmetic_unit_to_mux,F[2],Output);
endmodule
//F2 F1 F0 ALU operation
// 000 Complement A
// 001 and
// 010 xor
// 011 or
// 100 A+1
// 101 A+B
// 110 A-1
// 111 A-B
----------------------------------------------------------------------------------------------------------------
4 BIT LOGIC UNIT COMPONENT
----------------------------------------------------------------------------------------------------------------
module four_bit_logic_unit
#(parameter N=4)(
input [N-1:0]InA,
input [N-1:0]InB,
input [1:0]Control,
output [N-1:0]Output
);
genvar i;
generate
for(i=0;i begin: intantiate_logic_unit
one_bit_logic_function logic_unit_instance(InA[i],InB[i],Control,Output[i]);
end
endgenerate
endmodule
----------------------------------------------------------------------------------------------------------------
#(parameter N=4)(
input [N-1:0]InA,
input [N-1:0]InB,
input [1:0]Control,
output [N-1:0]Output
);
genvar i;
generate
for(i=0;i
one_bit_logic_function logic_unit_instance(InA[i],InB[i],Control,Output[i]);
end
endgenerate
endmodule
1 BIT LOGIC UNIT COMPONENT
----------------------------------------------------------------------------------------------------------------
module one_bit_logic_function(
input a,
input b,
input [1:0] Control,
output reg Output
);
always @*
begin
case (Control)
2'b00: Output = ~a;
2'b01: Output = a & b;
2'b10: Output = a ^ b;
2'b11: Output = a | b;
endcase
end
endmodule
----------------------------------------------------------------------------------------------------------------
DOWNLOAD FILES <=
FOUR BIT ARITHMETIC UNIT STRUCTURAL DESIGN
----------------------------------------------------------------------------------------------------------------
module four_bit_arithmetic_unit
#(parameter N=4)
(
input [N-1:0]InA,
input [N-1:0]InB,
input [1:0]Control,
output [N-1:0]Sum,
output C_out
);
//assign InA =assig_to_A;
wire [N-1:0]mux_to_addersub;
nbit_two_input_multiplexer mux_component(4'b0001,InB,Control[0],mux_to_addersub);
nbit_adder_subtractor add_subtractor_component(InA,mux_to_addersub,Control[1],Sum,C_out);
endmodule
//Control arithmetic function
// 00 A+1
// 01 A+B
// 10 A-1
// 11 A-B
----------------------------------------------------------------------------------------------------------------
FOUR BIT TWO INPUT MULTIPLEXER STRUCTURAL DESIGN
----------------------------------------------------------------------------------------------------------------
module nbit_two_input_multiplexer
#(parameter N=4)
(input [N-1:0]bin0,
input [N-1:0]bin1,
input sel,
output [N-1:0]mux_out);
genvar i;
generate
for (i=0;i
two_input_multiplexer mux(.bin0(bin0[i]),.bin1(bin1[i]),.sel(sel),.mux_out(mux_out[i]));
end
endgenerate
endmodule
----------------------------------------------------------------------------------------------------------------
1 BIT TWO INPUT MULTIPLEXER
----------------------------------------------------------------------------------------------------------------
module two_input_multiplexer(
input wire bin0,
input wire bin1,
input wire sel,
output mux_out
);
//if select is 0 chose bin0 otherwise bin1
assign mux_out = sel ? bin1 : bin0 ;
endmodule
----------------------------------------------------------------------------------------------------------------
ADDER SUBTRACTOR TOP MODULE
----------------------------------------------------------------------------------------------------------------
module nbit_adder_substractor
#(parameter N=4)
( input [N-1:0]InA,
input [N-1:0]InB,
input Control,
output [N-1:0]Sum,
output C_out
);
wire [N-1:0]xor_to_adder;
four_bit_LAC_adder adder_component(InA,xor_to_adder,Control,Sum,C_out);
nbit_xor_gate_control xor_componet(InB,Control,xor_to_adder);
endmodule
FOUR BIT CARRY LOOK AHEAD ADDER COMPONENT
----------------------------------------------------------------------------------------------------------------
module four_bit_LAC_adder(
input [3:0]InA,
input [3:0]InB,
input Cin,
output [3:0]sum,
output Cout );
wire [3:0]C_terms;
four_bit_LAC LAC_component(InA[3:0],InB[3:0],Cin,C_terms[3:0]);
nbit_full_adder full_adder_component(InA,InB,C_terms,sum,Cout);
endmodule
FOUR BIT CARRY LOOK AHEAD LOGIC COMPONENT
----------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------
module four_bit_LAC_adder(
input [3:0]InA,
input [3:0]InB,
input Cin,
output [3:0]sum,
output Cout );
wire [3:0]C_terms;
four_bit_LAC LAC_component(InA[3:0],InB[3:0],Cin,C_terms[3:0]);
nbit_full_adder full_adder_component(InA,InB,C_terms,sum,Cout);
endmodule
FOUR BIT CARRY LOOK AHEAD LOGIC COMPONENT
----------------------------------------------------------------------------------------------------------------
module four_bit_LAC(
input [3:0]InA,
input [3:0]InB,
input C_in,
output reg [3:0]C_terms
);
wire [3:0]G;
wire [3:0]P;
assign G[3:0] = InA[3:0] & InB[3:0] ;//carry look ahead generate
assign P[3:0] = InA[3:0] | InB[3:0] ;//carry look ahead propagate
always @*
begin
C_terms[0] = C_in;
C_terms[1] = G[0] | (P[0]& C_in);
C_terms[2] = G[1] | ( P[1] & G[0]) | (P[1] & P[0] & C_in);
C_terms[3] = G[2] | ( P[2]& G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C_in) ;
end
endmodule
FOUR BIT FULL ADDER
----------------------------------------------------------------------------------------------------------------
module nbit_full_adder
#(parameter N= 4)
(input [N-1:0]a,
input [N-1:0]b,
input [N-1:0]cin,
output [N-1:0]sum,
output cout
);
wire [N-2:0]not_connected;
genvar i;
generate
for(i=0;i
begin: full_adder_instantiation
if (i
begin
full_adder full_adder_i(.a(a[i]),.b(b[i]),.cin(cin[i]),.s(sum[i]),.cout(not_connected[i]));
end
else if(i==(N-1))
begin
full_adder full_adder_i(.a(a[i]),.b(b[i]),.cin(cin[i]),.s(sum[i]),.cout(cout));
end
end
endgenerate
endmodule
1 BIT FULL ADDER COMPONENT
----------------------------------------------------------------------------------------------------------------
module full_adder(
input a,
input b,
input cin,
output s,
output cout
);
wire to_xor,to_or0,to_or1;
half_adder half_adder_unit0(a,b,to_xor,to_or1);
half_adder half_adder_unit1(to_xor,cin,s,to_or0);
or_gate or_unit (to_or0,to_or1,cout);
endmodule
//cin a b c s
// 0 0 0 0 0
// 0 0 1 0 1
// 0 1 0 0 1
// 0 1 1 1 0
// 1 1 1 1 1
HALF ADDER COMPONENT
----------------------------------------------------------------------------------------------------------------
module full_adder(
input a,
input b,
input cin,
output s,
output cout
);
wire to_xor,to_or0,to_or1;
half_adder half_adder_unit0(a,b,to_xor,to_or1);
half_adder half_adder_unit1(to_xor,cin,s,to_or0);
or_gate or_unit (to_or0,to_or1,cout);
endmodule
//cin a b c s
// 0 0 0 0 0
// 0 0 1 0 1
// 0 1 0 0 1
// 0 1 1 1 0
// 1 1 1 1 1
HALF ADDER COMPONENT
----------------------------------------------------------------------------------------------------------------
module half_adder(
input a,
input b,
output s,
output c
);
xor_gate xorGate_unit(a,b,s);
and_gate andgate_unit(a,b,c);
endmodule
//
//a b c s
//0 0 0 0
//0 1 0 1
//1 0 0 1
//1 1 1 0
XOR GATE COMPONENT
----------------------------------------------------------------------------------------------------------------
module xor_gate(
input a,
input b,
output f
);
assign f= a ^ b;
endmodule
// 1 as long as both inputs are different
//a b f
//0 0 0
//0 1 1
//1 0 1
//1 1 0
AND GATE COMPONENT
----------------------------------------------------------------------------------------------------------------
module and_gate (input wire a,
input wire b,
output wire f
);
assign f = a & b;
endmodule
XOR GATE CONTROL
----------------------------------------------------------------------------------------------------------------
module nbit_xor_gate_control
#(parameter N = 4)
(
input [N-1:0] a,
input b,
output [N-1:0]f
);
genvar i;
generate
for(i=0;i
begin: xor_instantiation
xor_gate xor_i(.a(a[i]),.b(b),.f(f[i]));
end
endgenerate
endmodule
// 1 as long as both inputs are different
//a b f
//0 0 0
//0 1 1
//1 0 1
//1 1 0
TUTORIAL ON HOW TO ADD TIMING CONSTRAINTS IN A MODULE
SHIFTER ROTATOR CONSTRAINTS
---------------------------------------------------------------------------------------------------------------
TUTORIAL ON HOW TO ADD TIMING CONSTRAINTS IN A MODULE
SHIFTER ROTATOR CONSTRAINTS
---------------------------------------------------------------------------------------------------------------
#8I/Os_2
NET "Data_In[0]" LOC = "p94" ;
NET "Data_In[1]" LOC = "p93" ;
NET "Data_In[2]" LOC = "p92" ;
NET "Data_In[3]" LOC = "p91" ;
#8I/Os_2
NET "G[0]" LOC = "p51" ;
NET "G[1]" LOC = "p43" ;
NET "G[2]" LOC = "p44" ;
#16I/Os_1
NET "Output[0]" LOC = "p126" ;
NET "Output[1]" LOC = "p125" ;
NET "Output[2]" LOC = "p124" ;
NET "Output[3]" LOC = "p123" ;
NET "Data_In[0]" LOC = "p94" ;
NET "Data_In[1]" LOC = "p93" ;
NET "Data_In[2]" LOC = "p92" ;
NET "Data_In[3]" LOC = "p91" ;
#8I/Os_2
NET "G[0]" LOC = "p51" ;
NET "G[1]" LOC = "p43" ;
NET "G[2]" LOC = "p44" ;
#16I/Os_1
NET "Output[0]" LOC = "p126" ;
NET "Output[1]" LOC = "p125" ;
NET "Output[2]" LOC = "p124" ;
NET "Output[3]" LOC = "p123" ;
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