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Master module
library ieee;
use ieee.std_logic_1164.all;
entity vga_test is
port (
clk, reset: in std_logic;
sw: in std_logic_vector ( 2 downto 0 ) ;
hsync , vsync : out std_logic;
rgb : out std_logic_vector ( 2 downto 0 )
) ;
end vga_test ;
architecture arch of vga_test is
signal rgb_reg: std_logic_vector ( 2 downto 0) ;
signal video_on: std_logic ;
begin
-- i n s t a n t i a t e VGA s y n c c i r c u i t
vga_sync_unit : entity work.vga_sync(arch)
port map(clk=>clk, reset=>reset , hsync=>hsync ,
vsync=>vsync, video_on=>video_on,
p_tick=>open, pixel_x=>open, pixel_y=>open);
-- r g b b u f f e r
process (clk , reset)
begin
if reset='1' then
rgb_reg <= ( others => '0' ) ;
elsif (clk'event and clk='1') then
rgb_reg <= sw ;
end if ;
end process ;
rgb <= rgb_reg when video_on='1' else "000";
end arch;
Sync module
Library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vga_sync is
port (
clk, reset: in std_logic;
hsync , vsync : out std_logic ;
video_on, p_tick: out std_logic;
pixel_x , pixel_y : out std_logic_vector (9 downto 0)
) ;
end vga_sync ;
architecture arch of vga_sync is
-- VGA 6 4 0 - b y - 4 8 0 s y n c p a r a m e t e r s
constant HD: integer :=640; -- h o r i z o n t a l d is p l a y a r e a
constant HF: integer:=16 ; --h. f r o n t p o r c h
constant HB: integer:=48 ; --h. b a c k p o r c h
constant HR: integer:=96 ; --h. r e t r a c e
constant VD :integer :=480; -- v e r t i c a l d is p l a y a r e a
constant VF :integer:=10; -- v . f r o n t p o r c h
constant VB: integer :=33; -- v . b a c k p o r c h
constant VR :integer :=2; -- v . r e t r a c e
-- mod-2 c o u n t e r
signal mod2_reg, mod2_next : std_logic;
-- s y n c c o u n t e r s
signal v_count_reg , v_count_next : unsigned(9 downto 0) ;
signal h_count_reg , h_count_next : unsigned (9 downto 0 ) ;
-- o u t p u t b u f f e r
signal v_sync_reg , h_sync_reg : std_logic ;
signal v_sync_next , h_sync_next : std_logic;
-- s t a t u s signal
signal h_end , v_end , pixel_tick: std_logic;
-- r e g is t e r s
begin
process (clk , reset)
begin
if reset='1' then
mod2_reg <= '0' ;
v_count_reg <= ( others => '0' ) ;
h_count_reg <= ( others => '0' ) ;
v_sync_reg <= '0' ;
h_sync_reg <= '0' ;
elsif (clk'event and clk='1') then
mod2_reg <= mod2_next ;
v_count_reg <= v_count_next;
h_count_reg <= h_count_next;
v_sync_reg <= v_sync_next ;
h_sync_reg <= h_sync_next ;
end if ;
end process ;
-- mod-2 c i r c u i t t o g e n e r a t e 2 5 MHz e n a b l e t i c k
mod2_next <= not mod2_reg;
-- 2 5 MHz p i x e l t i c k
pixel_tick <= '1' when mod2_reg='1' else '0' ;
-- s t a t u s
h_end <=-- end of h o r i z o n t a l c o u n t e r
'1' when h_count_reg=(HD+HF+HB+HR-1) else --799
'0' ;
v_end <= -- end of v e r t i c a l c o u n t e r
'1' when v_count_reg=(VD+VF+VB+VR-1) else --524
'0' ;
-- mod-800 h o r i z o n t a l s y n c c o u n t e r
process (h_count_reg,h_end,pixel_tick)
begin
if pixel_tick='1' then -- 2 5 MHz t i c k
if h_end='1' then
h_count_next <= ( others => '0' ) ;
else
h_count_next <= h_count_reg + 1 ;
end if ;
else
h_count_next <= h_count_reg;
end if ;
end process ;
process (v_count_reg,h_end,v_end,pixel_tick)
begin
-- mod-525 v e r t i c a l s y n c c o u n t e r
if pixel_tick='1' and h_end='1' then
if (v_end='1') then
v_count_next <= ( others => '0' ) ;
else
v_count_next <= v_count_reg + 1 ;
end if ;
else
v_count_next <= v_count_reg;
end if ;
end process ;
-- h o r i z o n t a l and v e r t i c a l s y n c , b u f f e r e d t o a v o i d g l i t c h
h_sync_next <=
'1' when (h_count_reg >=(HD+HF)) --656
and (h_count_reg<=(HD+HF+HR-1)) else --751
'0';
v_sync_next <=
'1' when ( v_count_reg >= ( VD+VF ) ) --490
and (v_count_reg<=(VD+VF+VR-1)) else --491
'0' ;
-- v i d e o o n / o f f
video_on <=
'1' when (h_count_reg<HD) and (v_count_reg<VD) else
'0' ;
--o u t p u t signal
hsync <= h_sync_reg ;
vsync <= v_sync_reg ;
pixel_x <= std_logic_vector(h_count_reg);
pixel_y <= STD_LOGIC_VECTOR ( v_count_reg ) ;
p_tick <= pixel_tick;
end arch;
Constraint file
#Created by Constraints Editor (xc3s250e-tq144-4) - 2017/07/29
NET "clk" LOC = "P129"; #TNM_NET = clk;
TIMESPEC TS_clk = PERIOD "clk" 50 MHz HIGH 50%;
#8I/Os_2 (Input)
NET "reset" LOC = "p91" ;
#16I/Os_1 (output)
NET "hsync" LOC = "p126" ;
NET "vsync" LOC = "p125" ;
NET "rgb[0]" LOC = "p124" ;
NET "rgb[1]" LOC = "p123" ;
NET "rgb[2]" LOC = "p122" ;
#8I/Os_2
NET "sw[0]" LOC = "p94" ;
NET "sw[1]" LOC = "p93" ;
NET "sw[2]" LOC = "p92" ;
TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE
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