FPGA Verilog HALF and FULL ADDER circuit test Waveshare Xilinx Spartan 3 development board + code

This video is part of a series to design a Controlled Datapath using a structural approach in Verilog. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete vhdl video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP


HALF ADDER

 module half_adder(  
   input a,  
   input b,  
   output s,  
   output c  
   );  
 xor_gate xorGate_unit(.a(a),.b(b),.f(s) );  
 and_gate andgate_unit(.a(a),.b(b),.f(c));  
 endmodule  

 //a b c s   
 //0 0 0 0  
 //0 1 0 1  
 //1 0 0 1  
 //1 1 1 0       

FULL ADDER

 module full_adder(  
   input a,  
   input b,  
   input cin,    
       output s,  
       output cout  
   );  
 wire to_xor,to_or0,to_or1;  
 half_adder half_adder_unit0(.a(a),.b(b),.s(to_xor),.c(to_or1));  
 half_adder half_adder_unit1(.a(cin),.b(to_xor),.s(s),.c(to_or0));  
 or_gate  or_unit (.a(to_or0),.b(to_or1),.f(cout));  
 endmodule  

 //  
 //cin a b c s   
 // 0 0 0 0 0  
 // 0 0 1 0 1  
 // 0 1 0 0 1  
 // 0 1 1 1 0  
 // 1 1 1 1 1       

AND GATE MODULE

 module and_gate (input wire a,  
                               input wire b,  
                               output wire f  
          );   
 assign f = a & b;  
 endmodule  

XOR GATE MODULE

 module xor_gate(  
   input a,  
   input b,  
   output f  
   );  
 assign f= a ^ b;  
 endmodule  
 // 1 as long as both inputs are different  
 //a b f  
 //0 0 0  
 //0 1 1  
 //1 0 1  
 //1 1 0  

OR GATE MODULE

 module or_gate(  
       input wire a,  
   input wire b,  
   output wire f  
       );  
 assign f = a | b;  
 endmodule  
 //a b f  
 //0 0 0  
 //0 1 1  
 //1 0 1  
 //1 1 1  

FULL ADDER CONSTRAINT

 #8I/Os_2  
 NET "a" LOC = "p94" ;  
 NET "b" LOC = "p93" ;  
 NET "cin" LOC = "p92" ;  
 #16I/Os_1  
 NET "s" LOC = "p126" ;  
 NET "cout" LOC = "p125" ;  

HALF ADDER CONSTRAINT

 #8I/Os_2  
 NET "a" LOC = "p94" ;  
 NET "b" LOC = "p93" ;  
 #16I/Os_1  
 NET "s" LOC = "p126" ;  
 NET "c" LOC = "p125" ;