Verilog FPGA three input or gate Xilinx Spartan 3 development board

This video is part of a series to design a Controlled Datapath using a structural approach in Verilog. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete vhdl video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

MODULE

 module three_input_or_gate(  
   input wire a,  
   input wire b,  
   input wire c,  
   output wire f  
   );  
 assign f = a | b | c ;  
 endmodule  

Tutorial to add timing contraints

CONSTRAINT FILE

 #8I/Os_2  
 NET "a" LOC = "p94" ;  
 NET "b" LOC = "p93" ;  
 NET "c" LOC = "p92" ;  
 #16I/Os_1  
 NET "f" LOC = "p126" ;