FPGA Verilog Priority encoder circuit test Waveshare Xilinx Spartan 3 development board

The priority encoder has four requests, r [3], r [2], r [1], and r [0],
which are grouped as a single 4-bit r input, and r [4] has the highest priority. The output is the binary code of the highest-order request.

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PRIORITY ENCODER USING A CASE STATEMENT

 module prio_encoder_case  
   (  
   input wire [3:0] r,  
   output reg [2:0] y  
   );  
   always @*  
    case(r)  
      4'b1000, 4'b1001, 4'b1010, 4'b1011,  
      4'b1100, 4'b1101, 4'b1110, 4'b1111:  
       y = 3'b100;  
      4'b0100, 4'b0101, 4'b0110, 4'b0111:  
       y = 3'b011;  
      4'b0010, 4'b0011:  
       y = 3'b010;  
      4'b0001:  
       y = 3'b001;  
      4'b0000:   // default can also be used  
       y = 3'b000;  
    endcase  
 endmodule  

                           OTHER PRIORITY ENCODER APPROACHES

PRIORITY ENCODER WITH DON'T CARE CASE STATEMENT

 module prio_encoder_case  
   (  
   input wire [4:1] r,  
   output reg [2:0] y1, y2  
   );  
   // case statement  
   //  - each branch can contain multiple statements  
   //   with begin ... end delimiters  
   always @*  
    case(r)  
      4'b1000, 4'b1001, 4'b1010, 4'b1011,  
      4'b1100, 4'b1101, 4'b1110, 4'b1111:  
       y1 = 3'b100;  
      4'b0100, 4'b0101, 4'b0110, 4'b0111:  
       y1 = 3'b011;  
      4'b0010, 4'b0011:  
       y1 = 3'b010;  
      4'b0001:  
       y1 = 3'b001;  
      4'b0000:   // default can also be used  
       y1 = 3'b000;  
    endcase  
   // casez statement  
   always @*  
    casez(r)  
      4'b1???: y2 = 3'b100; // use ? for don't-care  
      4'b01??: y2 = 3'b011;  
      4'b001?: y2 = 3'b010;  
      4'b0001: y2 = 3'b001;  
      4'b0000: y2 = 3'b000; // default can also be used  
    endcase  
 endmodule  

PRIORITY ENCODER CASE STATEMENT HIGH IMPEDANCE

 module prio_encoder_casez  
   (  
   input wire [4:1] r,  
   output reg [2:0] y  
   );  
   always @*  
    casez(r)  
      4'b1???: y = 3'b100;  
      4'b01??: y = 3'b011;  
      4'b001?: y = 3'b010;  
      4'b0001: y = 3'b001;  
      4'b0000: y = 3'b000; // default can also be used  
    endcase  
 endmodule  

PRIORITY ENCODER IF STATEMENT

 module prio_encoder_if  
   (  
   input wire [4:1] r,  
   output reg [2:0] y  
   );  
   always @*  
    if (r[4]==1'b1)   // can be written as (r[4])  
      y = 3'b100;  
    else if (r[3]==1'b1) // can be written as (r[3])  
      y = 3'b011;  
    else if (r[2]==1'b1) // can be written as (r[2])  
      y = 3'b010;  
    else if (r[1]==1'b1) // can be written as (r[1])  
      y = 3'b001;  
    else  
      y = 3'b000;  
 endmodule  

PRIORITY ENCODER WITH COMPARATOR

 module prio_encoder_if  
   (  
   input wire [4:1] r,  
   output wire [2:0] y1,   
   output reg [2:0] y2  
   );  
   // Conditional operator  
   assign y1 = (r[4]) ? 3'b100 : // can also use (r[4]==1'b1)  
         (r[3]) ? 3'b011 :  
         (r[2]) ? 3'b010 :  
         (r[1]) ? 3'b001 :  
         3'b000;  
   // If statement  
   //  - each branch can contain multiple statements  
   //   with begin ... end delimiters  
   always @*  
    if (r[4])  
      y2 = 3'b100;  
    else if (r[3])  
      y2 = 3'b011;  
    else if (r[2])  
      y2 = 3'b010;  
    else if (r[1])  
      y2 = 3'b001;  
    else  
      y2 = 3'b000;  
 endmodule  

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