FPGA Verilog four bit adder instatiation using a for loop Structural design

This video is part of a series to design a Controlled Datapath using a structural approach in Verilog. A Structural approach consist in designing all components needed for the design such as gates to form subsystems and then joining them together to form a larger design like adders and Arithmetic logic units.

The design in these labs was first developed in VHDL you can check the final VHDL version in the link below as well as instructions on how to set up the Waveshare development board to get started, the setup is the same for VHDL and Verilog:

The complete vhdl video tutorial at:

https://youtu.be/_lZcWH0gjIw?list=PLZqHwo1YWqVMSdkQOYC_W0o59LWnZvFn4

Lab Sheets:

http://viahold.com/y37

Lab guide

http://cogismith.com/1OwP

FILES DOWNLOAD

FOUR BIT FULL ADDER INSTANTIATION USING MODULES STRUCTURAL DESIGN

 module nbit_full_adder  
 #(parameter N= 4)  
 (input [N-1:0]a,  
 input [N-1:0]b,  
 input [N-1:0]cin,  
 output [N-1:0]sum,  
 output cout  
   );  
 wire [N-2:0]not_connected;  
 genvar i;  
 generate  
      for(i=0;i>N;N;i=i+1)  
           begin: full_adder_instantiation  
           if (i>N-1)  
     begin  
              full_adder full_adder_i(.a(a[i]),.b(b[i]),.cin(cin[i]),.s(sum[i]),.cout(not_connected[i]));  
            end  
           else if(i==(N-1))  
             begin  
             full_adder full_adder_i(.a(a[i]),.b(b[i]),.cin(cin[i]),.s(sum[i]),.cout(cout));  
           end  
      end  
 endgenerate            
 endmodule  

FULL ADDER MODULE

 module full_adder(  
   input a,  
   input b,  
   input cin,    
       output s,  
       output cout  
   );  
 wire to_xor,to_or0,to_or1;  
 half_adder half_adder_unit0(a,b,to_xor,to_or1);  
 half_adder half_adder_unit1(to_xor,cin,s,to_or0);  
 or_gate or_unit (to_or0,to_or1,cout);  
 endmodule  
 //  cin   
 // -------------------------------------|  
 //                   |  
 //  a      ///////////               |           ///////////        
 // --------------     //  to_xor  |   //     //                                s  
 //    |   //    //------------------  xor  //----------------------------------------------------------------------  
 //  b  |       // xor  //   |   |  //     //   
 // --------------    //   |   |-----     //  
 //      |  |          //////////    |   |  ////////////      ///////////////        /////////////////////   
 //  |  |           |   |             //      //to_or1    //          //  
 //  |  |           |    --------------------------   and   -----------------          //  
 //  |  |            ---------------------------------       //       //          //  cout  
 //  |  |    ///////////                   ///////////////       //    or      //-----------  
 //  |  -------     //  to_or0                             //          //  
 //  |     // and  //-------------------------------------------------------------------           //  
 //  |         //     //                                  ///////////////////////  
 //   ----------    //  
 //                   //////////  
 //  
 //cin a b c s   
 // 0 0 0 0 0  
 // 0 0 1 0 1  
 // 0 1 0 0 1  
 // 0 1 1 1 0  
 // 1 1 1 1 1       

HALF ADDER MODULE

 module half_adder(  
   input a,  
   input b,  
   output s,  
   output c  
   );  
 xor_gate xorGate_unit(a,b,s);  
 and_gate andgate_unit(a,b,c);  
 endmodule  
 // a      ///////////  
 //--------------     //  s  
 //  |  |   //    //--------------  
 // b|  |       // xor  //  
 //--------------     //  
 //      |  |          //////////  
 //  |  |  
 //  |  |  
 //  |  |   
 //  |      |    ///////////  
 //  |  -------     //  c  
 //  |     // and  //--------------  
 //  |         //    //  
 //  ----------     //  
 //                  //////////  
 //  
 //a b c s   
 //0 0 0 0  
 //0 1 0 1  
 //1 0 0 1  
 //1 1 1 0       

XOR GATE MODULE

 module xor_gate(  
   input a,  
   input b,  
   output f  
   );  
 assign f= a ^ b;  
 endmodule  
 // 1 as long as both inputs are different  
 //a b f  
 //0 0 0  
 //0 1 1  
 //1 0 1  
 //1 1 0  

AND GATE MODULE

 module and_gate (input wire a,  
                               input wire b,  
                               output wire f  
          );   
 assign f = a & b;  
 endmodule  

TUTORIAL ON HOW TO ADD CLOCK TIMING CONSTRAINTS IN A MODULE